mirror of https://github.com/m-labs/artiq.git
ad9154: merge csr spaces
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4d87f0e9e0
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1193ba4bf4
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@ -28,17 +28,17 @@ def ad9516_read(addr: TInt32) -> TInt32:
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@syscall(flags={"nounwind", "nowrite"})
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def jesd_enable(en: TInt32) -> TNone:
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def ad9154_jesd_enable(en: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def jesd_ready() -> TInt32:
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def ad9154_jesd_ready() -> TInt32:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def jesd_prbs(prbs: TInt32) -> TNone:
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def ad9154_jesd_prbs(prbs: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@ -85,13 +85,13 @@ class AD9154:
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@kernel
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def jesd_enable(self, en):
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"""Enables the JESD204B core startup sequence."""
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jesd_enable(en)
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ad9154_jesd_enable(en)
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@kernel
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def jesd_ready(self):
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"""Returns `True` if the JESD links are up."""
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return jesd_ready()
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return ad9154_jesd_ready()
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@kernel
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def jesd_prbs(self, prbs):
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jesd_prbs(prbs)
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ad9154_jesd_prbs(prbs)
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@ -11,7 +11,6 @@ ps = JESD204BPhysicalSettings(
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m=4, # converters
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n=16, # bits/converter
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np=16, # bits/sample
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sc=250*1e6, # data clock, unused: FIXME
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)
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ts = JESD204BTransportSettings(
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f=2, # octets/(lane and frame)
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@ -21,8 +20,6 @@ ts = JESD204BTransportSettings(
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)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_checksum = jesd_settings.get_configuration_data()[-1]
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jesd_data_freq = 250e6
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jesd_linerate = 5e9
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# external clk=2000MHz
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# pclock=250MHz
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# deviceclock_fpga=500MHz
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@ -441,10 +441,48 @@ class _PhaserCRG(Module, AutoCSR):
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]
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, rtio_crg):
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ad9154_spi = platform.request("ad9154_spi")
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self.submodules.spi = spi_csr.SPIMaster(ad9154_spi)
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self.comb += [
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ad9154_spi.en.eq(1),
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platform.request("ad9154_txen", 0).eq(1),
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platform.request("ad9154_txen", 1).eq(1),
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]
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sync_pads = platform.request("ad9154_sync")
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jesd_sync = Signal()
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self.specials += DifferentialInput(
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sync_pads.p, sync_pads.n, jesd_sync)
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_linerate = 5e9
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jesd_refclk_freq = 500e6
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rtio_freq = 125*1000*1000
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jesd_phys = [JESD204BPhyTX(
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rtio_crg.refclk, jesd_refclk_freq,
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platform.request("ad9154_jesd", i),
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jesd_linerate, rtio_freq, i) for i in range(4)]
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self.submodules += jesd_phys
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for jesd_phy in jesd_phys:
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platform.add_period_constraint(
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jesd_phy.gtx.cd_tx.clk,
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40/jesd_linerate*1e9)
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platform.add_false_path_constraints(
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rtio_crg.cd_rtio.clk,
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jesd_phy.gtx.cd_tx.clk)
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self.submodules.jesd_core = JESD204BCoreTX(
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jesd_phys, jesd_settings, converter_data_width=32)
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self.comb += self.jesd_core.start.eq(jesd_sync)
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self.submodules.jesd_control = JESD204BCoreTXControl(self.jesd_core)
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class Phaser(_NIST_Ions):
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mem_map = {
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"ad9154_spi": 0x50000000,
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"jesd_control": 0x40000000,
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"ad9154": 0x50000000,
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}
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mem_map.update(_NIST_Ions.mem_map)
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@ -474,17 +512,6 @@ class Phaser(_NIST_Ions):
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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ad9154_spi = self.platform.request("ad9154_spi")
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self.submodules.ad9154_spi = spi_csr.SPIMaster(ad9154_spi)
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self.register_kernel_cpu_csrdevice("ad9154_spi")
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self.config["AD9154_DAC_CS"] = 1 << 0
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self.config["AD9154_CLK_CS"] = 1 << 1
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self.comb += [
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ad9154_spi.en.eq(1),
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self.platform.request("ad9154_txen", 0).eq(1),
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self.platform.request("ad9154_txen", 1).eq(1),
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]
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += sawgs
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@ -500,36 +527,13 @@ class Phaser(_NIST_Ions):
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# jesd_sysref = Signal()
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# self.specials += DifferentialInput(
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# sysref_pads.p, sysref_pads.n, jesd_sysref)
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sync_pads = platform.request("ad9154_sync")
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jesd_sync = Signal()
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self.specials += DifferentialInput(
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sync_pads.p, sync_pads.n, jesd_sync)
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16, sc=250*1e6)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_linerate = 5e9
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jesd_refclk_freq = 500e6
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rtio_freq = 125*1000*1000
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jesd_phys = [JESD204BPhyTX(
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self.rtio_crg.refclk, jesd_refclk_freq,
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platform.request("ad9154_jesd", i),
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jesd_linerate, rtio_freq, i) for i in range(4)]
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self.submodules += jesd_phys
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for jesd_phy in jesd_phys:
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platform.add_period_constraint(
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jesd_phy.gtx.cd_tx.clk,
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40/jesd_linerate*1e9)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk,
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jesd_phy.gtx.cd_tx.clk)
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self.submodules.jesd_core = JESD204BCoreTX(
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jesd_phys, jesd_settings, converter_data_width=32)
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self.comb += self.jesd_core.start.eq(jesd_sync)
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self.submodules.jesd_control = JESD204BCoreTXControl(self.jesd_core)
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self.register_kernel_cpu_csrdevice("jesd_control")
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to_rtio = ClockDomainsRenamer({"sys": "rtio"})
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self.submodules.ad9154 = to_rtio(AD9154(platform, self.rtio_crg))
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self.register_kernel_cpu_csrdevice("ad9154")
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self.config["AD9154_DAC_CS"] = 1 << 0
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self.config["AD9154_CLK_CS"] = 1 << 1
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for i, ch in enumerate(sawgs):
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conv = getattr(self.jesd_core.transport.sink,
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conv = getattr(self.ad9154.jesd_core.transport.sink,
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"converter{}".format(i))
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# while at 5 GBps, take every second sample... FIXME
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self.comb += conv.eq(Cat(ch.o[::2]))
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@ -54,19 +54,19 @@ uint8_t ad9516_read(uint16_t addr)
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return ad9154_spi_data_read_read();
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}
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void jesd_enable(int en)
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void ad9154_jesd_enable(int en)
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{
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jesd_control_enable_write(en);
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ad9154_jesd_control_enable_write(en);
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}
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int jesd_ready(void)
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int ad9154_jesd_ready(void)
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{
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return jesd_control_ready_read();
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return ad9154_jesd_control_ready_read();
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}
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void jesd_prbs(int p)
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void ad9154_jesd_prbs(int p)
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{
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jesd_control_prbs_config_write(p);
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ad9154_jesd_control_prbs_config_write(p);
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}
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#endif /* CONFIG_AD9154_DAC_CS */
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@ -10,9 +10,9 @@ uint8_t ad9154_read(uint16_t addr);
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void ad9516_write(uint16_t addr, uint8_t data);
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uint8_t ad9516_read(uint16_t addr);
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void jesd_enable(int en);
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int jesd_ready(void);
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void jesd_prbs(int p);
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void ad9154_jesd_enable(int en);
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int ad9154_jesd_ready(void);
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void ad9154_jesd_prbs(int p);
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#endif
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#endif
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@ -144,9 +144,9 @@ static const struct symbol runtime_exports[] = {
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{"ad9154_read", &ad9154_read},
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{"ad9516_write", &ad9516_write},
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{"ad9516_read", &ad9516_read},
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{"jesd_enable", &jesd_enable},
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{"jesd_ready", &jesd_ready},
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{"jesd_prbs", &jesd_prbs},
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{"ad9154_jesd_enable", &ad9154_jesd_enable},
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{"ad9154_jesd_ready", &ad9154_jesd_ready},
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{"ad9154_jesd_prbs", &ad9154_jesd_prbs},
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#endif
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/* end */
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