ttl: improve clockgen doc

artiq/coredevice/ttl.py

@@ -253,6 +253,10 @@ class TTLClockGen(AutoDB):
         accumulator is connected to the TTL line. Setting the frequency tuning
         word has the additional effect of setting the phase accumulator to
         0x800000.
+
+        Due to the way the clock generator operates, frequency tuning words
+        that are not powers of two cause jitter of one RTIO clock cycle at the
+        output.
         """
         syscall("ttl_clock_set", now_mu(), self.channel, frequency)
         self.previous_timestamp = now_mu()

artiq/gateware/rtio/phy/ttl_simple.py

@@ -89,6 +89,7 @@ class ClockGen(Module):
         self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
         self.sync.rio_phy += [
             acc.eq(acc + ftw),
+            # rtlink takes precedence over regular acc increments
             If(self.rtlink.o.stb,
                 If(self.rtlink.o.data != 0,
                     # known phase on frequency write: at rising edge