mirror of https://github.com/m-labs/artiq.git
drtio: input fixes
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@ -230,6 +230,7 @@ class RTController(Module):
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)
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fsm.act("READ",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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rt_packet_read_request.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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@ -238,6 +239,7 @@ class RTController(Module):
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)
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fsm.act("GET_READ_REPLY",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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If(rt_packet.read_not,
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load_read_reply.eq(1),
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NextState("IDLE")
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@ -106,6 +106,8 @@ class IOS(Module):
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self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
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def add_input(self, n, channel):
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rt_packet = self.rt_packet
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interface = channel.interface.i
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if interface is None:
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return
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