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artiq
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drtio: input fixes

This commit is contained in:
Sebastien Bourdeauducq 2017-03-14 14:14:43 +08:00
parent 856a64f6d2
commit 56fd9b3b4b
2 changed files with 4 additions and 0 deletions
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2
artiq/gateware/drtio/rt_controller_master.py
View File

@ -230,6 +230,7 @@ class RTController(Module):
)
fsm.act("READ",
i_status_wait_status.eq(1),
rt_packet.read_not_ack.eq(1),
rt_packet_read_request.eq(1),
rt_packet.sr_stb.eq(1),
If(rt_packet.sr_ack,
@ -238,6 +239,7 @@ class RTController(Module):
)
fsm.act("GET_READ_REPLY",
i_status_wait_status.eq(1),
rt_packet.read_not_ack.eq(1),
If(rt_packet.read_not,
load_read_reply.eq(1),
NextState("IDLE")

2
artiq/gateware/drtio/rt_ios_satellite.py
View File

@ -106,6 +106,8 @@ class IOS(Module):
self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
def add_input(self, n, channel):
rt_packet = self.rt_packet
interface = channel.interface.i
if interface is None:
return