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gateware: work around ISE/Vivado bugs with very wide shifts.

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This commit is contained in:
whitequark 2017-03-16 03:11:10 +00:00
parent f5aa73b8fa
commit 4b14887ddb
1 changed files with 4 additions and 2 deletions
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6
artiq/gateware/rtio/dma.py
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@ -14,7 +14,7 @@ class WishboneReader(Module):
self.bus = bus
aw = len(bus.adr)
dw = len(bus.dat_w)
dw = len(bus.dat_w)
self.sink = stream.Endpoint([("address", aw)])
self.source = stream.Endpoint([("data", dw)])
@ -106,7 +106,9 @@ class RawSlicer(Module):
If(load_buf, Case(level,
{i: buf[i*g:(i+in_size)*g].eq(self.sink.data)
for i in range(out_size)})),
If(shift_buf, buf.eq(buf >> self.source_consume*g))
If(shift_buf, Case(self.source_consume,
{i: buf.eq(buf[i*g:])
for i in range(out_size)})),
]
fsm = FSM(reset_state="FETCH")