drtio: fixes, basic TTL working in simulation

artiq/gateware/drtio/core.py

@@ -45,7 +45,7 @@ class DRTIOSatellite(Module):
 
 
 class DRTIOMaster(Module):
-    def __init__(self, transceiver):
+    def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
         self.submodules.link_layer = link_layer.LinkLayer(
             transceiver.encoder, transceiver.decoders)
         self.comb += [
@@ -53,7 +53,8 @@ class DRTIOMaster(Module):
             self.link_layer.rx_ready.eq(transceiver.rx_ready)
         ]
         self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
-        self.submodules.rt_controller = rt_controller.RTController(self.rt_packets)
+        self.submodules.rt_controller = rt_controller.RTController(
+            self.rt_packets, channel_count, fine_ts_width)
 
     def get_csrs(self):
         return self.rt_controller.get_csrs()

artiq/gateware/drtio/rt_controller.py

@@ -25,16 +25,16 @@ class _KernelCSRs(AutoCSR):
 
         self.tsc_correction = CSRStorage(64)
         self.set_time = CSR()
-        self.underflow_margin = CSRStorage(16, reset=50)
+        self.underflow_margin = CSRStorage(16, reset=200)
 
-        self.get_fifo_space = CSR()
-        self.dbg_fifo_space = CSRStatus(16)
-        self.dbg_last_timestamp = CSRStatus(64)
-        self.reset_channel_status = CSR()
+        self.o_get_fifo_space = CSR()
+        self.o_dbg_fifo_space = CSRStatus(16)
+        self.o_dbg_last_timestamp = CSRStatus(64)
+        self.o_reset_channel_status = CSR()
 
 
 class RTController(Module):
-    def __init__(self, rt_packets, channel_count=1024):
+    def __init__(self, rt_packets, channel_count, fine_ts_width):
         self.kcsrs = _KernelCSRs()
 
         self.submodules.counter = RTIOCounter(64)
@@ -93,8 +93,8 @@ class RTController(Module):
 
         # TODO: collision, replace, busy
         cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
-        cond_underflow = (self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
-                          < self.counter.value_sys)
+        cond_underflow = ((self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
+                           >> fine_ts_width) < self.counter.value_sys)
         cond_fifo_emptied = ((last_timestamps.dat_r
                               < self.counter.value_sys - self.kcsrs.underflow_margin.storage)
                              & (last_timestamps.dat_r != 0))
@@ -109,7 +109,7 @@ class RTController(Module):
                     NextState("WRITE")
                 )
             ),
-            If(self.kcsrs.get_fifo_space.re,
+            If(self.kcsrs.o_get_fifo_space.re,
                 NextState("GET_FIFO_SPACE")
             )
         )
@@ -154,9 +154,9 @@ class RTController(Module):
         )
 
         self.comb += [
-            self.kcsrs.dbg_fifo_space.status.eq(fifo_spaces.dat_r),
-            self.kcsrs.dbg_last_timestamp.status.eq(last_timestamps.dat_r),
-            If(self.kcsrs.reset_channel_status.re,
+            self.kcsrs.o_dbg_fifo_space.status.eq(fifo_spaces.dat_r),
+            self.kcsrs.o_dbg_last_timestamp.status.eq(last_timestamps.dat_r),
+            If(self.kcsrs.o_reset_channel_status.re,
                 fifo_spaces.dat_w.eq(0),
                 fifo_spaces.we.eq(1),
                 last_timestamps.dat_w.eq(0),

artiq/gateware/drtio/rt_packets.py

@@ -495,7 +495,10 @@ class RTPacketMaster(Module):
         tx_fsm.act("FIFO_SPACE",
             tx_dp.send("fifo_space_request", channel=write_channel),
             tx_dp.stb.eq(1),
-            If(tx_dp.done, NextState("IDLE_WRITE"))
+            If(tx_dp.done,
+                wfifo.re.eq(1),
+                NextState("IDLE_WRITE")
+            )
         )
         tx_fsm.act("ECHO",
             tx_dp.send("echo_request"),

artiq/test/gateware/drtio/test_full_stack.py

@@ -37,7 +37,7 @@ class DummyRXSynchronizer:
 class DUT(Module):
     def __init__(self, nwords):
         self.ttl = Signal()
-        self.transceivers = DummyTransceiverPair(2)
+        self.transceivers = DummyTransceiverPair(nwords)
         
         self.submodules.master = DRTIOMaster(self.transceivers.alice)
 
@@ -52,10 +52,36 @@ class TestFullStack(unittest.TestCase):
         dut = DUT(2)
         kcsrs = dut.master.rt_controller.kcsrs    
 
-        def get_fifo_level():
-            for i in range(8):
-                yield from kcsrs.counter_update.write(1)
-                print((yield from kcsrs.counter.read()))
+        def get_fifo_space():
+            yield from kcsrs.o_get_fifo_space.write(1)
+            yield
+            while (yield from kcsrs.o_status.read()) & 1:
+                yield
+            return (yield from kcsrs.o_dbg_fifo_space.read())
 
-        run_simulation(dut, get_fifo_level(),
-            {"sys": 8, "rtio": 5, "rtio_rx": 5})
+        def test():
+            print((yield from get_fifo_space()))
+            yield from kcsrs.o_timestamp.write(550)
+            yield from kcsrs.o_data.write(1)
+            yield from kcsrs.o_we.write(1)
+            yield
+            status = 1
+            while status:
+                status = yield from kcsrs.o_status.read()
+                print("status after write:", status)
+                yield
+            yield from kcsrs.o_timestamp.write(600)
+            yield from kcsrs.o_data.write(0)
+            yield from kcsrs.o_we.write(1)
+            yield
+            status = 1
+            while status:
+                status = yield from kcsrs.o_status.read()
+                print("status after write:", status)
+                yield
+            for i in range(40):
+                yield
+            #print((yield from get_fifo_space()))
+
+        run_simulation(dut, test(),
+            {"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")