mirror of https://github.com/m-labs/artiq.git
drtio: various fixes
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cce29e8b83
commit
9752ffe3d1
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@ -15,17 +15,17 @@ class DRTIOSatellite(Module):
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]
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx.aux_frame,
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tx_aux_frame=self.link_layer.tx_aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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tx_aux_ack=self.link_layer.tx_aux_ack,
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tx_rt_frame=self.link_layer.tx_rt_frame,
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tx_rt_data=self.link_layer.tx_rt_data,
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rx_aux_stb=rx_synchronizer.sync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.sync(self.link_layer.rx_aux_frame),
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rx_aux_data=rx_synchronizer.sync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.sync(self.link_layer.rx_rt_frame),
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rx_rt_data=rx_synchronizer.sync(self.link_layer.rx_rt_data)
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rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame),
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rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame),
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rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)
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)
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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@ -33,6 +33,16 @@ class DRTIOSatellite(Module):
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self.submodules.iot = ClockDomainsRenamer("rtio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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# TODO: remote resets
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio.rst.eq(ResetSignal("rtio")),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.rst.eq(ResetSignal("rtio")),
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]
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class DRTIOMaster(Module):
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def __init__(self):
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@ -16,9 +16,10 @@ class IOT(Module):
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)
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for n, channel in enumerate(channels):
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data_width = rtlink.get_data_width(channel.interface)
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address_width = rtlink.get_address_width(channel.interface)
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fine_ts_width = rtlink.get_fine_ts_width(channel.interface)
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interface = channel.interface.o
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data_width = rtlink.get_data_width(interface)
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address_width = rtlink.get_address_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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assert fine_ts_width <= max_fine_ts_width
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# FIFO
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@ -47,7 +48,7 @@ class IOT(Module):
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If(~fifo.writable, rt_packets.write_overflow.eq(1)),
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If(rt_packets.write_underflow_ack,
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rt_packets.write_underflow.eq(0)),
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If(rt_packets.timestamp[max_fine_ts_width:] < (tsc + 4),
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If(rt_packets.write_timestamp[max_fine_ts_width:] < (tsc + 4),
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rt_packets.write_underflow.eq(1)
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)
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)
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@ -56,7 +57,7 @@ class IOT(Module):
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if address_width:
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self.comb += fifo_in.address.eq(rt_packets.write_address)
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self.comb += fifo_in.timestamp.eq(
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rt_packets.timestamp[max_fine_ts_width-fine_ts_width:])
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rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:])
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# FIFO read
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self.sync += [
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@ -8,6 +8,8 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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class GTX_1000BASE_BX10(Module):
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rtio_clk_freq = 62.5e6
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq):
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self.submodules.encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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@ -33,7 +35,7 @@ class GTX_1000BASE_BX10(Module):
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tx_init = GTXInit(sys_clk_freq, False)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio")(
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GTXInit(62.5e6, True))
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GTXInit(self.rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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self.comb += tx_init.cplllock.eq(cplllock), \
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rx_init.cplllock.eq(cplllock), \
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@ -166,7 +168,7 @@ class GTX_1000BASE_BX10(Module):
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self.decoders[1].input.eq(rxdata[10:])
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]
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clock_aligner = BruteforceClockAligner(0b0011111000, 62.5e6)
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clock_aligner = BruteforceClockAligner(0b0011111000, self.rtio_clk_freq)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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@ -193,7 +195,7 @@ class RXSynchronizer(Module, AutoCSR):
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.cd_rtio_delayed = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtio_delayed = ClockDomain(reset_less=True)
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mmcm_output = Signal()
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mmcm_fb = Signal()
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@ -226,7 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
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Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk)
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]
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def sync(self, signal):
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def resync(self, signal):
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delayed = Signal.like(signal, related=signal)
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synchronized = Signal.like(signal, related=signal)
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self.sync.rtio_delayed += delayed.eq(signal)
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@ -157,7 +157,7 @@ class BruteforceClockAligner(Module):
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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comma_seen_reset = PulseSynchronizer("sys", "rx")
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comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += comma_seen_reset
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self.sync.rtio_rx += \
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If(comma_seen_reset.o,
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