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https://github.com/m-labs/artiq.git
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drtio: add RX link layer, fixes, simple loopback demo
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@ -1,5 +1,5 @@
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from functools import reduce
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from operator import xor
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from operator import xor, or_
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from migen import *
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@ -59,8 +59,6 @@ class LinkLayerTX(Module):
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self.rt_frame = Signal()
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self.rt_data = Signal(8*nwords)
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self.transceiver_data = Signal(10*nwords)
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# # #
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# Idle and auxiliary traffic use special characters excluding
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@ -88,7 +86,7 @@ class LinkLayerTX(Module):
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self.aux_ack.eq(~self.rt_frame)
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]
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for i in range(nwords):
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scrambled_ctl = scrambler.o[i*3:i*3+3]
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scrambled_ctl = aux_scrambler.o[i*3:i*3+3]
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self.sync += [
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encoder.k[i].eq(1),
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If(scrambled_ctl == 7,
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@ -100,15 +98,18 @@ class LinkLayerTX(Module):
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# Real-time traffic uses data characters and is framed by the special
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# characters of auxiliary traffic. RT traffic is also scrambled.
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rt_scrambler = Scrambler(8*nwords)
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rt_scrambler = CEInserter()(Scrambler(8*nwords))
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self.submodules += rt_scrambler
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self.comb += rt_scrambler.i.eq(self.rt_data)
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self.comb += [
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rt_scrambler.i.eq(self.rt_data),
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rt_scrambler.ce.eq(self.rt_frame)
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]
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rt_frame_r = Signal()
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self.sync += [
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rt_frame_r.eq(self.rt_frame),
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If(rt_frame_r,
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[k.eq(0) for k in encoder.k],
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[d.eq(self.rt_data[i*8:i*8+8]) for i, d in enumerate(encoder.d)]
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[d.eq(rt_scrambler.o[i*8:i*8+8]) for i, d in enumerate(encoder.d)]
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)
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]
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@ -134,3 +135,51 @@ class LinkLayerTX(Module):
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link_init_counter.eq(0)
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)
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]
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class LinkLayerRX(Module):
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def __init__(self, decoders):
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nwords = len(decoders)
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# nwords must be a power of 2
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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self.rt_frame = Signal()
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self.rt_data = Signal(8*nwords)
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# # #
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aux_descrambler = CEInserter()(Descrambler(2*nwords))
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rt_descrambler = CEInserter()(Descrambler(8*nwords))
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self.submodules += aux_descrambler, rt_descrambler
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self.comb += [
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self.aux_frame.eq(~aux_descrambler.o[2]),
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self.aux_data.eq(
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Cat(*[aux_descrambler.o[3*i:3*i+2] for i in range(nwords)])),
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self.rt_data.eq(rt_descrambler.o),
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]
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link_init_d = Signal()
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rt_frame_d = Signal()
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self.sync += [
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self.link_init.eq(link_init_d),
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self.rt_frame.eq(rt_frame_d)
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]
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self.comb += [
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If(decoders[0].k,
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If((decoders[0].d == K(28, 7)) | (decoders[0].d == K(29, 7)),
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link_init_d.eq(1)
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),
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aux_descrambler.ce.eq(1)
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).Else(
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rt_frame_d.eq(1),
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rt_descrambler.ce.eq(1)
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),
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aux_descrambler.i.eq(Cat(*[d.d >> 5 for d in decoders])),
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rt_descrambler.i.eq(Cat(*[d.d for d in decoders]))
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]
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84
artiq/test/gateware/drtio/test_link_layer.py
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84
artiq/test/gateware/drtio/test_link_layer.py
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@ -0,0 +1,84 @@
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import unittest
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from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio.link_layer import *
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def process(dut, seq):
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rseq = []
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def pump():
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yield dut.i.eq(seq[0])
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yield
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for w in seq[1:]:
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yield dut.i.eq(w)
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yield
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rseq.append((yield dut.o))
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yield
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rseq.append((yield dut.o))
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run_simulation(dut, pump())
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return rseq
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class TestScrambler(unittest.TestCase):
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def test_roundtrip(self):
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seq = list(range(256))*3
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq)
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self.assertNotEqual(seq, scrambled_seq)
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self.assertEqual(seq, descrambled_seq)
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def test_resync(self):
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seq = list(range(256))
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq[20:])
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self.assertEqual(seq[100:], descrambled_seq[80:])
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class Loopback(Module):
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def __init__(self, nwords):
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ks = [Signal() for k in range(nwords)]
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ds = [Signal(8) for d in range(nwords)]
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encoder = SimpleNamespace(k=ks, d=ds)
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decoders = [SimpleNamespace(k=k, d=d) for k, d in zip(ks, ds)]
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self.submodules.tx = LinkLayerTX(encoder)
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self.submodules.rx = LinkLayerRX(decoders)
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class TestLinkLayer(unittest.TestCase):
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def test_packets(self):
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dut = Loopback(4)
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rt_packets = [
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[0x12459970, 0x9938cdef, 0x12340000],
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[0xabcdef00, 0x12345678],
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[0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344]
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]
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def transmit_rt_packets():
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for packet in rt_packets:
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yield dut.tx.rt_frame.eq(1)
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for data in packet:
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yield dut.tx.rt_data.eq(data)
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yield
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yield dut.tx.rt_frame.eq(0)
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yield
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# flush
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for i in range(20):
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yield
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rx_rt_packets = []
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@passive
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def receive_rt_packets():
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while True:
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packet = []
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rx_rt_packets.append(packet)
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while not (yield dut.rx.rt_frame):
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yield
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while (yield dut.rx.rt_frame):
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packet.append((yield dut.rx.rt_data))
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yield
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run_simulation(dut, [transmit_rt_packets(), receive_rt_packets()])
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for packet in rx_rt_packets:
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print(" ".join("{:08x}".format(x) for x in packet))
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@ -1,35 +0,0 @@
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import unittest
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from migen import *
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from artiq.gateware.drtio.link_layer import Scrambler, Descrambler
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def process(dut, seq):
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rseq = []
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def pump():
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yield dut.i.eq(seq[0])
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yield
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for w in seq[1:]:
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yield dut.i.eq(w)
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yield
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rseq.append((yield dut.o))
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yield
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rseq.append((yield dut.o))
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run_simulation(dut, pump())
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return rseq
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class TestScrambler(unittest.TestCase):
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def test_roundtrip(self):
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seq = list(range(256))*3
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq)
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self.assertNotEqual(seq, scrambled_seq)
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self.assertEqual(seq, descrambled_seq)
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def test_resync(self):
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seq = list(range(256))
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq[20:])
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self.assertEqual(seq[100:], descrambled_seq[80:])
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