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https://github.com/m-labs/artiq.git
synced 2024-12-28 12:48:26 +08:00
runtime: support for targets without RTIO log channel
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parent
3c5a62243d
commit
0c49679984
@ -226,6 +226,7 @@ class NIST_CLOCK(_NIST_Ions):
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ofifo_depth=512,
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ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -304,6 +305,7 @@ class NIST_QC2(_NIST_Ions):
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ofifo_depth=512,
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ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -212,6 +212,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=64, ififo_depth=64))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -123,6 +123,7 @@ pub extern fn input_data(channel: u32) -> u32 {
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}
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}
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#[cfg(has_rtio_log)]
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pub fn log(timestamp: i64, data: &[u8]) {
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unsafe {
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csr::rtio::chan_sel_write(csr::CONFIG_RTIO_LOG_CHANNEL);
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@ -144,3 +145,6 @@ pub fn log(timestamp: i64, data: &[u8]) {
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csr::rtio::o_we_write(1);
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}
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}
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#[cfg(not(has_rtio_log))]
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pub fn log(timestamp: i64, data: &[u8]) {}
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