Florent Kermarrec 44dc76e42e Add serial Wishbone bridge ... Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3		2017-08-21 12:22:05 -04:00
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amp	gateware: use new MiSoC Wishbone address system	2017-07-13 19:16:49 +08:00
drtio	drtio: multilink transceiver interface	2017-07-18 13:27:33 +08:00
dsp	Revert "sawg: advance dds 1/2 by one sample group"	2017-07-04 17:55:19 +02:00
rtio	artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect	2017-07-04 10:48:06 +02:00
serwb	Add serial Wishbone bridge	2017-08-21 12:22:05 -04:00
targets	sayma_amc: connect RTM serial and second serial	2017-08-20 19:01:55 -04:00
test	sawg: confirm smooth(order=3)	2017-07-07 11:36:03 +02:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py	Merge remote-tracking branch 'm-labs/phaser2' into phaser2	2016-12-02 14:11:56 +01:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
spi.py	spi: fix xfers with full data_width (closes #615)	2017-01-03 19:51:14 +01:00