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https://github.com/m-labs/artiq.git
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drtio: add false paths between sys and transceiver clocks
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4b97b9f8ce
commit
5d145ff912
@ -11,9 +11,8 @@ class GTX_20X(Module):
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# The transceiver clock on clock_pads must be at the RTIO clock
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# frequency when clock_div2=False, and 2x that frequency when
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# clock_div2=True.
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def __init__(self, platform,
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clock_pads, tx_pads, rx_pads,
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sys_clk_freq, clock_div2=False):
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
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clock_div2=False):
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self.submodules.encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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self.decoders = [ClockDomainsRenamer("rtio_rx")(
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@ -22,6 +21,11 @@ class GTX_20X(Module):
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self.rx_ready = Signal()
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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# # #
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refclk = Signal()
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@ -50,9 +54,7 @@ class GTX_20X(Module):
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self.comb += tx_init.cplllock.eq(cplllock), \
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rx_init.cplllock.eq(cplllock)
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txoutclk = Signal()
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txdata = Signal(20)
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rxoutclk = Signal()
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rxdata = Signal(20)
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self.specials += \
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Instance("GTXE2_CHANNEL",
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@ -88,7 +90,7 @@ class GTX_20X(Module):
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=txoutclk,
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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@ -134,7 +136,7 @@ class GTX_20X(Module):
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i_RXDDIEN=1,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=rxoutclk,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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p_RXCDR_CFG=0x03000023FF10100020,
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@ -165,7 +167,7 @@ class GTX_20X(Module):
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio = ClockDomain()
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self.specials += [
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Instance("BUFG", i_I=txoutclk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
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AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
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]
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rx_reset_deglitched = Signal()
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@ -173,12 +175,9 @@ class GTX_20X(Module):
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self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
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self.clock_domains.cd_rtio_rx = ClockDomain()
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self.specials += [
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Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk),
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
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]
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platform.add_period_constraint(txoutclk, 1e9/self.rtio_clk_freq)
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platform.add_period_constraint(rxoutclk, 1e9/self.rtio_clk_freq)
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platform.add_false_path_constraints(txoutclk, rxoutclk)
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self.comb += [
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txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),
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@ -59,7 +59,6 @@ class Master(MiniSoC, AMPSoC):
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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platform=platform,
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clock_pads=platform.request("sgmii_clock"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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@ -70,7 +69,6 @@ class Master(MiniSoC, AMPSoC):
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.register_extension(fmc_clock_io)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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platform=platform,
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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@ -80,6 +78,13 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.csr_devices.append("drtio")
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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rtio_channels = []
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for i in range(8):
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phy = ttl_simple.Output(platform.request("user_led", i))
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@ -165,7 +165,6 @@ class Satellite(Module):
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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platform=platform,
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clock_pads=platform.request("sgmii_clock"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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@ -176,7 +175,6 @@ class Satellite(Module):
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.register_extension(fmc_clock_io)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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platform=platform,
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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@ -188,6 +186,14 @@ class Satellite(Module):
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self.submodules.drtio = DRTIOSatellite(
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self.transceiver, self.rx_synchronizer, rtio_channels)
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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sys_clock_pads,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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def build(self, *args, **kwargs):
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self.platform.build(self, *args, **kwargs)
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