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https://github.com/m-labs/artiq.git
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soc,runtime: support TTL override
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parent
6c094b500d
commit
b2af0f6cc3
@ -1,2 +1,2 @@
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from artiq.gateware.rtio.core import Channel, RTIO
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from artiq.gateware.rtio.moninj import Monitor
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from artiq.gateware.rtio.moninj import MonInj
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@ -247,12 +247,20 @@ class _InputManager(Module):
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class Channel:
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def __init__(self, interface, probes=[], ofifo_depth=64, ififo_depth=64):
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def __init__(self, interface, probes=[], overrides=[],
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ofifo_depth=64, ififo_depth=64):
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self.interface = interface
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self.probes = probes
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self.overrides = overrides
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self.ofifo_depth = ofifo_depth
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self.ififo_depth = ififo_depth
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@classmethod
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def from_phy(cls, phy, **kwargs):
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probes = getattr(phy, "probes", [])
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overrides = getattr(phy, "overrides", [])
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return cls(phy.rtlink, probes, overrides, **kwargs)
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class _KernelCSRs(AutoCSR):
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def __init__(self, chan_sel_width,
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@ -1,6 +1,6 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.cdc import BusSynchronizer
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from migen.genlib.cdc import BusSynchronizer, MultiReg
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class Monitor(Module, AutoCSR):
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@ -11,7 +11,7 @@ class Monitor(Module, AutoCSR):
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max_probe_len = max(flen(p) for cp in chan_probes for p in cp)
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self.chan_sel = CSRStorage(bits_for(len(chan_probes)-1))
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self.probe_sel = CSRStorage(bits_for(max_chan_probes-1))
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self.probe_value = CSRStatus(max_probe_len)
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self.value = CSRStatus(max_probe_len)
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# # #
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@ -25,5 +25,42 @@ class Monitor(Module, AutoCSR):
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cp_sys.append(vs.o)
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cp_sys += [0]*(max_chan_probes-len(cp))
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chan_probes_sys.append(Array(cp_sys)[self.probe_sel.storage])
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self.comb += self.probe_value.status.eq(
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self.comb += self.value.status.eq(
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Array(chan_probes_sys)[self.chan_sel.storage])
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class Injector(Module, AutoCSR):
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def __init__(self, channels):
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chan_overrides = [c.overrides for c in channels]
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max_chan_overrides = max(len(co) for co in chan_overrides)
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max_override_len = max(flen(o) for co in chan_overrides for o in co)
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self.chan_sel = CSRStorage(bits_for(len(chan_overrides)-1))
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self.override_sel = CSRStorage(bits_for(max_chan_overrides-1))
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self.value = CSR(max_override_len)
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# # #
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chan_overrides_sys = []
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for n_channel, co in enumerate(chan_overrides):
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co_sys = []
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for n_override, o in enumerate(co):
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# We do the clock domain transfer with a simple double-latch.
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# Software has to ensure proper timing of any strobe signal etc.
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# to avoid problematic glitches.
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o_sys = Signal.like(o)
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self.specials += MultiReg(o_sys, o, "rio")
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self.sync += If(self.value.re & (self.chan_sel.storage == n_channel)
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& (self.override_sel.storage == n_override),
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o_sys.eq(self.value.r))
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co_sys.append(o_sys)
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co_sys += [0]*(max_chan_overrides-len(co))
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chan_overrides_sys.append(Array(co_sys)[self.override_sel.storage])
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self.comb += self.value.w.eq(
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Array(chan_overrides_sys)[self.chan_sel.storage])
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class MonInj(Module, AutoCSR):
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def __init__(self, channels):
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self.submodules.mon = Monitor(channels)
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self.submodules.inj = Injector(channels)
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@ -8,10 +8,23 @@ class Output(Module):
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def __init__(self, pad):
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self.rtlink = rtlink.Interface(rtlink.OInterface(1))
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self.probes = [pad]
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override_en = Signal()
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override_o = Signal()
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self.overrides = [override_en, override_o]
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# # #
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self.sync.rio_phy += If(self.rtlink.o.stb, pad.eq(self.rtlink.o.data))
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pad_k = Signal()
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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pad_k.eq(self.rtlink.o.data)
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),
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If(override_en,
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pad.eq(override_o)
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).Else(
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pad.eq(pad_k)
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)
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]
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class Inout(Module):
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@ -19,6 +32,10 @@ class Inout(Module):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(2, 2),
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rtlink.IInterface(1))
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override_en = Signal()
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override_o = Signal()
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override_oe = Signal()
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self.overrides = [override_en, override_o, override_oe]
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self.probes = []
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# # #
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@ -27,10 +44,21 @@ class Inout(Module):
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self.specials += ts.get_tristate(pad)
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sensitivity = Signal(2)
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self.sync.rio_phy += If(self.rtlink.o.stb,
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If(self.rtlink.o.address == 0, ts.o.eq(self.rtlink.o.data[0])),
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If(self.rtlink.o.address == 1, ts.oe.eq(self.rtlink.o.data[0])),
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o_k = Signal()
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oe_k = Signal()
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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If(self.rtlink.o.address == 0, o_k.eq(self.rtlink.o.data[0])),
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If(self.rtlink.o.address == 1, oe_k.eq(self.rtlink.o.data[0])),
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),
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If(override_en,
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ts.o.eq(override_o),
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ts.oe.eq(override_oe)
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).Else(
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ts.o.eq(o_k),
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ts.oe.eq(oe_k)
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)
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]
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
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sensitivity.eq(self.rtlink.o.data))
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@ -20,6 +20,19 @@ enum {
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MONINJ_REQ_TTLSET = 2
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};
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enum {
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MONINJ_TTL_MODE_EXP = 0,
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MONINJ_TTL_MODE_1 = 1,
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MONINJ_TTL_MODE_0 = 2,
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MONINJ_TTL_MODE_IN = 3
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};
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enum {
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MONINJ_TTL_OVERRIDE_ENABLE = 0,
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MONINJ_TTL_OVERRIDE_O = 1,
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MONINJ_TTL_OVERRIDE_OE = 2
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};
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static struct udp_pcb *listen_pcb;
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struct monitor_reply {
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@ -28,8 +41,6 @@ struct monitor_reply {
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long long int ttl_overrides;
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};
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static long long int ttl_overrides;
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static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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{
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struct monitor_reply reply;
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@ -38,16 +49,20 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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reply.ttl_levels = 0;
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reply.ttl_oes = 0;
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reply.ttl_overrides = 0;
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for(i=0;i<RTIO_TTL_COUNT;i++) {
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rtio_mon_chan_sel_write(i);
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rtio_mon_probe_sel_write(0);
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if(rtio_mon_probe_value_read())
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rtio_moninj_mon_chan_sel_write(i);
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rtio_moninj_mon_probe_sel_write(0);
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if(rtio_moninj_mon_value_read())
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reply.ttl_levels |= 1LL << i;
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rtio_mon_probe_sel_write(1);
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if(rtio_mon_probe_value_read())
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rtio_moninj_mon_probe_sel_write(1);
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if(rtio_moninj_mon_value_read())
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reply.ttl_oes |= 1LL << i;
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rtio_moninj_inj_chan_sel_write(i);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_ENABLE);
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if(rtio_moninj_inj_value_read())
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reply.ttl_overrides |= 1LL << i;
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}
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reply.ttl_overrides = ttl_overrides;
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reply_p = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct monitor_reply), PBUF_RAM);
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if(!reply_p) {
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@ -61,10 +76,38 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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static void moninj_ttlset(int channel, int mode)
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{
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if(mode)
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ttl_overrides |= (1LL << channel);
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else
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ttl_overrides &= ~(1LL << channel);
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rtio_moninj_inj_chan_sel_write(channel);
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switch(mode) {
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case MONINJ_TTL_MODE_EXP:
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_ENABLE);
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rtio_moninj_inj_value_write(0);
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break;
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case MONINJ_TTL_MODE_1:
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_O);
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rtio_moninj_inj_value_write(1);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_OE);
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rtio_moninj_inj_value_write(1);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_ENABLE);
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rtio_moninj_inj_value_write(1);
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break;
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case MONINJ_TTL_MODE_0:
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_O);
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rtio_moninj_inj_value_write(0);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_OE);
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rtio_moninj_inj_value_write(1);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_ENABLE);
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rtio_moninj_inj_value_write(1);
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break;
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case MONINJ_TTL_MODE_IN:
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_OE);
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rtio_moninj_inj_value_write(0);
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rtio_moninj_inj_override_sel_write(MONINJ_TTL_OVERRIDE_ENABLE);
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rtio_moninj_inj_value_write(1);
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break;
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default:
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log("unknown TTL mode %d", mode);
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break;
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}
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}
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static void moninj_recv(void *arg, struct udp_pcb *upcb, struct pbuf *req,
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@ -37,7 +37,7 @@ class NIST_QC1(MiniSoC, AMPSoC):
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 13,
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"kernel_cpu": 14,
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"rtio_mon": 15
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"rtio_moninj": 15
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}
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csr_map.update(MiniSoC.csr_map)
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mem_map = {
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@ -66,16 +66,15 @@ class NIST_QC1(MiniSoC, AMPSoC):
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for i in range(2):
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phy = ttl_simple.Inout(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes,
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ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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for i in range(16):
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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@ -84,14 +83,14 @@ class NIST_QC1(MiniSoC, AMPSoC):
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"rio")
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phy = RT2WB(7, self.dds.bus)
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.submodules.rtio_mon = rtio.Monitor(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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platform.add_platform_command("""
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@ -91,26 +91,25 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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for i in range(2):
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phy = ttl_simple.Inout(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes,
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ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Inout(platform.request("xtrig", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(16):
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("ext_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(2, 5):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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@ -119,14 +118,14 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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"rio")
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phy = RT2WB(7, self.dds.bus)
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.submodules.rtio_mon = rtio.Monitor(rtio_channels)
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self.submodules.rtio_mon = rtio.MonInj(rtio_channels)
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# CPU connections
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rtio_csrs = self.rtio.get_csrs()
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