gateware: simplify the CRI arbiter to use a plain mux.

artiq/firmware/ksupport/lib.rs

@@ -301,18 +301,6 @@ extern fn dma_erase(name: CSlice<u8>) {
     send(&DmaEraseRequest(name));
 }
 
-unsafe fn rtio_arb_dma() {
-    csr::rtio::arb_req_write(0);
-    csr::rtio_dma::arb_req_write(1);
-    while csr::rtio_dma::arb_gnt_read() == 0 {}
-}
-
-unsafe fn rtio_arb_regular() {
-    csr::rtio_dma::arb_req_write(0);
-    csr::rtio::arb_req_write(1);
-    while csr::rtio::arb_gnt_read() == 0 {}
-}
-
 extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
     let name = str::from_utf8(name.as_ref()).unwrap();
 
@@ -326,10 +314,10 @@ extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
                 csr::rtio_dma::base_address_write(ptr as u64);
                 csr::rtio_dma::time_offset_write(timestamp as u64);
 
-                rtio_arb_dma();
+                csr::cri_con::selected_write(1);
                 csr::rtio_dma::enable_write(1);
                 while csr::rtio_dma::enable_read() != 0 {}
-                rtio_arb_regular();
+                csr::cri_con::selected_write(0);
 
                 true
             }

artiq/gateware/rtio/core.py

@@ -291,7 +291,6 @@ class Core(Module, AutoCSR):
         self.reset = CSR()
         self.reset_phy = CSR()
         self.async_error = CSR(2)
-        self.comb += self.cri.arb_gnt.eq(1)
 
         # Clocking/Reset
         # Create rsys, rio and rio_phy domains based on sys and rtio

artiq/gateware/rtio/cri.py

@@ -17,9 +17,6 @@ commands = {
 
 
 layout = [
-    ("arb_req", 1, DIR_M_TO_S),
-    ("arb_gnt", 1, DIR_S_TO_M),
-
     ("cmd", 2, DIR_M_TO_S),
     # 8 MSBs of chan_sel are used to select core
     ("chan_sel", 24, DIR_M_TO_S),
@@ -49,9 +46,6 @@ class Interface(Record):
 
 class KernelInitiator(Module, AutoCSR):
     def __init__(self, cri=None):
-        self.arb_req = CSRStorage()
-        self.arb_gnt = CSRStatus()
-
         self.chan_sel = CSRStorage(24)
         self.timestamp = CSRStorage(64)
 
@@ -77,9 +71,6 @@ class KernelInitiator(Module, AutoCSR):
         # # #
 
         self.comb += [
-            self.cri.arb_req.eq(self.arb_req.storage),
-            self.arb_gnt.status.eq(self.cri.arb_gnt),
-
             self.cri.cmd.eq(commands["nop"]),
             If(self.o_we.re, self.cri.cmd.eq(commands["write"])),
             If(self.i_request.re, self.cri.cmd.eq(commands["read"])),
@@ -132,7 +123,7 @@ class CRIDecoder(Module):
         self.comb += Case(selected, cases)
 
 
-class CRIArbiter(Module):
+class CRIArbiter(Module, AutoCSR):
     def __init__(self, masters=2, slave=None):
         if isinstance(masters, int):
             masters = [Interface() for _ in range(masters)]
@@ -141,18 +132,18 @@ class CRIArbiter(Module):
         self.masters = masters
         self.slave = slave
 
+        self.selected = CSRStorage(len(masters).bit_length())
+
         # # #
 
         if len(masters) == 1:
             self.comb += masters[0].connect(slave)
         else:
-            selected = Signal(max=len(masters))
-
             # mux master->slave signals
             for name, size, direction in layout:
                 if direction == DIR_M_TO_S:
                     choices = Array(getattr(m, name) for m in masters)
-                    self.comb += getattr(slave, name).eq(choices[selected])
+                    self.comb += getattr(slave, name).eq(choices[self.selected.storage])
 
             # connect slave->master signals
             for name, size, direction in layout:
@@ -160,20 +151,13 @@ class CRIArbiter(Module):
                     source = getattr(slave, name)
                     for i, m in enumerate(masters):
                         dest = getattr(m, name)
-                        if name == "arb_gnt":
-                            self.comb += dest.eq(source & (selected == i))
-                        else:
-                            self.comb += dest.eq(source)
-
-            # select master
-            self.sync += \
-                If(~slave.arb_req,
-                    [If(m.arb_req, selected.eq(i)) for i, m in enumerate(masters)]
-                )
-
+                        self.comb += dest.eq(source)
 
 class CRIInterconnectShared(Module):
     def __init__(self, masters=2, slaves=2):
         shared = Interface()
         self.submodules.arbiter = CRIArbiter(masters, shared)
         self.submodules.decoder = CRIDecoder(slaves, shared)
+
+    def get_csrs(self):
+        return self.arbiter.get_csrs()

artiq/gateware/rtio/dma.py

@@ -244,9 +244,6 @@ class TimeOffset(Module, AutoCSR):
 
 class CRIMaster(Module, AutoCSR):
     def __init__(self):
-        self.arb_req = CSRStorage()
-        self.arb_gnt = CSRStatus()
-
         self.error_status = CSRStatus(3)  # same encoding as RTIO status
         self.error_underflow_reset = CSR()
         self.error_sequence_error_reset = CSR()
@@ -261,11 +258,6 @@ class CRIMaster(Module, AutoCSR):
 
         # # #
 
-        self.comb += [
-            self.cri.arb_req.eq(self.arb_req.storage),
-            self.arb_gnt.status.eq(self.cri.arb_gnt)
-        ]
-
         error_set = Signal(2)
         for i, rcsr in enumerate([self.error_underflow_reset, self.error_sequence_error_reset]):
             # bit 0 is RTIO wait and always 0 here

artiq/gateware/targets/kc705_dds.py

@@ -151,6 +151,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.rtio.cri, self.rtio_dma.cri],
             [self.rtio_core.cri])
+        self.csr_devices.append("cri_con")
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")