M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00
Code Issues Projects Releases Wiki Activity

fir: size hint for pre-adder

Browse Source
This commit is contained in:
Robert Jördens 2016-12-20 17:57:47 +01:00
parent f310274e39
commit cfb66117af
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/dsp/fir.py
View File

@ -83,7 +83,10 @@ class FIR(Module):
else:
self.comb += o0.eq(o + m)
assert js[0] - delay >= 0
self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
xs = [x[j - delay] for j in js]
s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
self.comb += s.eq(sum(xs))
self.sync += m.eq(c*s)
# symmetric rounding
if shift:
self.comb += o.eq((1 << shift - 1) - 1)
@ -136,7 +139,10 @@ class ParallelFIR(Module):
else:
self.comb += o0.eq(o + m)
assert js[0] - delay >= 0
self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
xs = [x[j - delay] for j in js]
s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
self.comb += s.eq(sum(xs))
self.sync += m.eq(c*s)
# symmetric rounding
if shift:
self.comb += o.eq((1 << shift - 1) - 1)