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sawg: fix clr width

This commit is contained in:
Robert Jördens 2017-05-22 17:46:55 +02:00
parent 253ee950f6
commit 4901cb9a8a
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/dsp/sawg.py
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@ -84,7 +84,7 @@ class SplineParallelDDS(SplineParallelDUC):
class Config(Module):
def __init__(self, width):
self.clr = Signal(4, reset=0b1111)
self.clr = Signal(3, reset=0b111)
self.iq_en = Signal(2, reset=0b01)
self.limits = [[Signal((width, True), reset=-(1 << width - 1)),
Signal((width, True), reset=(1 << width - 1) - 1)]