mirror of https://github.com/m-labs/artiq.git
rtio: add one register level for rio and rio_phy resets
* This should give Vivado some wiggle room during PnR. * It needs three new clock domains which is ugly. But since AsyncResetSynchronizer can only drive clock domains resets directly there seems to be no other way to add one register level currently.
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@ -308,18 +308,28 @@ class Core(Module, AutoCSR):
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cmd_reset_phy.attr.add("no_retiming")
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio_rst = ClockDomain()
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self.clock_domains.cd_rio_phy_rst = ClockDomain()
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self.clock_domains.cd_rio_no_rst = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(cmd_reset)
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self.cd_rsys.rst.eq(cmd_reset),
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self.cd_rio_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio_no_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_rio_rst, cmd_reset),
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AsyncResetSynchronizer(self.cd_rio_phy_rst, cmd_reset_phy),
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]
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self.sync.rio_no_rst += [
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self.cd_rio.rst.eq(self.cd_rio_rst.rst),
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self.cd_rio_phy.rst.eq(self.cd_rio_phy_rst.rst),
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio, cmd_reset)
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self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio_phy, cmd_reset_phy)
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# Managers
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self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
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