mirror of https://github.com/m-labs/artiq.git
gateware: remove one stray CRI arbiter remnant.
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464202d0aa
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17b5388259
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@ -37,7 +37,6 @@ class RTController(Module):
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def __init__(self, rt_packet, channel_count, fine_ts_width):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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self.comb += self.cri.arb_gnt.eq(1)
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# protocol errors
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err_unknown_packet_type = Signal()
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@ -45,7 +44,7 @@ class RTController(Module):
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signal_fifo_space_timeout = Signal()
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err_fifo_space_timeout = Signal()
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self.sync.sys_with_rst += [
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If(self.csrs.protocol_error.re,
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If(self.csrs.protocol_error.re,
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If(self.csrs.protocol_error.r[0], err_unknown_packet_type.eq(0)),
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If(self.csrs.protocol_error.r[1], err_packet_truncated.eq(0)),
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If(self.csrs.protocol_error.r[2], err_fifo_space_timeout.eq(0))
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@ -70,7 +69,7 @@ class RTController(Module):
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tsc_correction = Signal(64)
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self.csrs.tsc_correction.storage.attr.add("no_retiming")
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self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
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self.comb += [
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self.comb += [
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rt_packet.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.csrs.set_time.w.eq(rt_packet.set_time_stb)
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