mirror of https://github.com/m-labs/artiq.git
sawg: wire up all HBF outputs, latency compensation in phys, simplify
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@ -5,7 +5,7 @@ from misoc.interconnect.stream import Endpoint
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from misoc.cores.cordic import Cordic
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from .accu import PhasedAccu
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from .tools import eqh, Delay, SatAddMixin
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from .tools import eqh, SatAddMixin
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from .spline import Spline
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from .fir import ParallelHBFUpsampler, halfgen4_cascade
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@ -14,44 +14,10 @@ _Widths = namedtuple("_Widths", "t a p f")
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_Orders = namedtuple("_Orders", "a p f")
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class ParallelDDS(Module):
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def __init__(self, widths, parallelism=1, a_delay=0):
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self.i = Endpoint([("x", widths.a), ("y", widths.a),
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("f", widths.f), ("p", widths.f), ("clr", 1)])
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class SplineParallelDUC(Module):
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def __init__(self, widths, orders, parallelism=1, **kwargs):
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self.parallelism = parallelism
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self.widths = widths
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###
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accu = PhasedAccu(widths.f, parallelism)
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cordic = [Cordic(width=widths.a, widthz=widths.p, guard=None,
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eval_mode="pipelined") for i in range(parallelism)]
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self.xo = [c.xo for c in cordic]
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self.yo = [c.yo for c in cordic]
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a_delay += accu.latency
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xy_delay = Delay(2*widths.a, max(0, a_delay))
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z_delay = Delay(parallelism*widths.p, max(0, -a_delay))
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self.submodules += accu, xy_delay, z_delay, cordic
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self.latency = max(0, a_delay) + cordic[0].latency
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self.gain = cordic[0].gain
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self.comb += [
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xy_delay.i.eq(Cat(self.i.x, self.i.y)),
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z_delay.i.eq(Cat(zi[-widths.p:]
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for zi in accu.o.payload.flatten())),
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eqh(accu.i.p, self.i.p),
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accu.i.f.eq(self.i.f),
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accu.i.clr.eq(self.i.clr),
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accu.i.stb.eq(self.i.stb),
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self.i.ack.eq(accu.i.ack),
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accu.o.ack.eq(1),
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[Cat(c.xi, c.yi).eq(xy_delay.o) for c in cordic],
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Cat(c.zi for c in cordic).eq(z_delay.o),
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]
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class SplineParallelDUC(ParallelDDS):
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def __init__(self, widths, orders, **kwargs):
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p = Spline(order=orders.p, width=widths.p)
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f = Spline(order=orders.f, width=widths.f)
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self.f = f.tri(widths.t)
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@ -59,27 +25,41 @@ class SplineParallelDUC(ParallelDDS):
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self.submodules += p, f
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self.ce = Signal(reset=1)
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self.clr = Signal()
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super().__init__(widths._replace(p=len(self.p.a0), f=len(self.f.a0)),
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**kwargs)
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self.latency += f.latency
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###
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accu = PhasedAccu(len(self.f.a0), parallelism)
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cordic = [Cordic(width=widths.a, widthz=len(self.p.a0), guard=None,
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eval_mode="pipelined") for i in range(parallelism)]
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self.submodules += accu, cordic
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self.xi = [c.xi for c in cordic]
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self.yi = [c.yi for c in cordic]
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self.xo = [c.xo for c in cordic]
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self.yo = [c.yo for c in cordic]
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self.latency = cordic[0].latency
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self.gain = cordic[0].gain
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self.f.latency += accu.latency + self.latency
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self.p.latency += accu.latency + self.latency
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###
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assert p.latency == f.latency
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self.comb += [
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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eqh(self.i.f, f.o.a0),
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eqh(self.i.p, p.o.a0),
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self.i.stb.eq(p.o.stb | f.o.stb),
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eqh(accu.i.f, f.o.a0),
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eqh(accu.i.p, p.o.a0),
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accu.i.stb.eq(p.o.stb | f.o.stb),
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accu.o.ack.eq(1),
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[eqh(c.zi, zi) for c, zi in
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zip(cordic, accu.o.payload.flatten())]
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]
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assert p.latency == 1
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self.sync += [
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self.i.clr.eq(0),
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accu.i.clr.eq(0),
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If(p.i.stb,
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self.i.clr.eq(self.clr),
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accu.i.clr.eq(self.clr),
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),
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]
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@ -91,12 +71,14 @@ class SplineParallelDDS(SplineParallelDUC):
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self.submodules += a
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super().__init__(widths._replace(a=len(self.a.a0)), orders, **kwargs)
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self.a.latency += self.latency
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###
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self.comb += [
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a.o.ack.eq(self.ce),
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eqh(self.i.x, a.o.a0),
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self.i.y.eq(0),
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[eqh(x, a.o.a0) for x in self.xi],
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[y.eq(0) for y in self.yi],
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]
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@ -151,12 +133,11 @@ class Channel(Module, SatAddMixin):
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hbf = [ParallelHBFUpsampler(coeff, width=width, shift=17)
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for i in range(2)]
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self.submodules.b = b = SplineParallelDUC(
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widths._replace(a=len(a1.xo[0]), f=widths.f - width), orders,
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parallelism=parallelism, a_delay=-a1.latency-hbf[0].latency)
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widths._replace(a=len(hbf[0].o[0]), f=widths.f - width), orders,
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parallelism=parallelism)
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cfg = Config(widths.a)
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u = Spline(width=widths.a, order=orders.a)
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du = Delay(width, a1.latency + hbf[0].latency + b.latency - u.latency)
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self.submodules += cfg, u, du, hbf
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self.submodules += cfg, u, hbf
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self.u = u.tri(widths.t)
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self.i = [cfg.i, self.u, a1.a, a1.f, a1.p, a2.a, a2.f, a2.p, b.f, b.p]
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self.i_names = "cfg u a1 f1 p1 a2 f2 p2 f0 p0".split()
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@ -166,9 +147,23 @@ class Channel(Module, SatAddMixin):
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self.widths = widths
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self.orders = orders
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self.parallelism = parallelism
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self.latency = a1.latency + hbf[0].latency + b.latency + 2
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self.cordic_gain = a1.gain*b.gain
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self.u.latency += 1
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b.p.latency += 2
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b.f.latency += 2
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a_latency_delta = hbf[0].latency + b.latency + 2
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for a in a1, a2:
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a.a.latency += a_latency_delta
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a.p.latency += a_latency_delta
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a.f.latency += a_latency_delta
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self.latency = max(_.latency for _ in self.i[1:])
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for i in self.i[1:]:
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i.latency -= self.latency
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assert i.latency <= 0
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cfg.i.latency = 0
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###
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self.comb += [
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@ -177,8 +172,8 @@ class Channel(Module, SatAddMixin):
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b.ce.eq(cfg.ce),
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u.o.ack.eq(cfg.ce),
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Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
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b.i.x.eq(hbf[0].o[0]), # FIXME: rip up
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b.i.y.eq(hbf[1].o[0]),
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Cat(b.xi).eq(Cat(hbf[0].o)),
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Cat(b.yi).eq(Cat(hbf[1].o)),
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]
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self.sync += [
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hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
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@ -187,14 +182,16 @@ class Channel(Module, SatAddMixin):
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hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
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limits=cfg.limits[1],
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clipped=cfg.clipped[1])),
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eqh(du.i, u.o.a0),
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]
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# wire up outputs and q_{i,o} exchange
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for o, x, y in zip(self.o, b.xo, self.y_in):
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self.sync += [
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o.eq(self.sat_add(
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du.o, Mux(cfg.iq_en[0], x, 0), Mux(cfg.iq_en[1], y, 0),
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limits=cfg.limits[2], clipped=cfg.clipped[2])),
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u.o.a0[-len(o):],
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Mux(cfg.iq_en[0], x, 0),
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Mux(cfg.iq_en[1], y, 0),
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limits=cfg.limits[2],
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clipped=cfg.clipped[2])),
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]
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def connect_y(self, buddy):
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@ -37,6 +37,7 @@ class Spline(Module):
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enumerate(self.i.payload.layout[::-1])]
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layout.reverse()
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i = Endpoint(layout)
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i.latency = self.latency
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self.comb += [
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self.i.stb.eq(i.stb),
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i.ack.eq(self.i.ack),
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@ -16,7 +16,8 @@ class Channel(_ChannelPHY):
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_ChannelPHY.__init__(self, *args, **kwargs)
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self.phys = []
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for i in self.i:
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload),
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delay=-i.latency))
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self.comb += [
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i.stb.eq(rl.o.stb),
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rl.o.busy.eq(~i.ack),
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