mirror of https://github.com/m-labs/artiq.git
gateware: add cri_con CSRs to all DMA-capable targets
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5e3aef45dc
commit
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@ -100,9 +100,9 @@ _ams101_dac = [
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class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"cri_con": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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@ -21,6 +21,7 @@ from artiq import __version__ as artiq_version
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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@ -114,6 +115,7 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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def main():
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@ -156,6 +156,7 @@ class AD9154(Module, AutoCSR):
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class Phaser(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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# "rtio_dma": 0x30000000,
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"mailbox": 0x70000000,
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@ -240,6 +241,7 @@ class Phaser(MiniSoC, AMPSoC):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri], # , self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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