mirror of https://github.com/m-labs/artiq.git
kc705_drtio_master: pretend drtio is rtio
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de065b7578
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@ -16,7 +16,7 @@ from artiq import __version__ as artiq_version
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"kdrtio": 0x20000000, # (shadow @0xa0000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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@ -41,7 +41,7 @@ class Master(MiniSoC, AMPSoC):
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.register_kernel_cpu_csrdevice("kdrtio", self.drtio.get_kernel_csrs())
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self.register_kernel_cpu_csrdevice("rtio", self.drtio.get_kernel_csrs())
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self.csr_devices.append("drtio")
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