mirror of https://github.com/m-labs/artiq.git
drtio: fix satellite transceiver clocking
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c39394b4d5
commit
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@ -45,26 +45,14 @@ class Satellite(BaseSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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if cfg == "simple_gbe":
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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clock_pads=platform.request("sgmii_clock"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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transceiver = gtx_7series.GTX_1000BASE_BX10
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elif cfg == "sawg_3g":
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# 3Gb link, 150MHz RTIO clock
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.add_extension(ad9154_fmc_ebz)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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@ -73,8 +61,16 @@ class Satellite(BaseSoC):
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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transceiver = gtx_7series.GTX_3G
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else:
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raise ValueError
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self.submodules.transceiver = transceiver(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=self.clk_freq)
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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self.transceiver.rtio_clk_freq, initial_phase=180.0)
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self.submodules.drtio = DRTIOSatellite(
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