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targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance
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@ -45,6 +45,18 @@ class _RTIOCRG(Module, AutoCSR):
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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rtio_half_internal_clk = Signal()
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self.specials += Instance("BUFR",
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p_BUFR_DIVIDE="2", i_CE=1, i_CLR=0,
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i_I=rtio_internal_clk,
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o_O=rtio_half_internal_clk)
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rtio_half_external_clk = Signal()
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self.specials += Instance("BUFR",
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p_BUFR_DIVIDE="2", i_CE=1, i_CLR=0,
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i_I=rtio_external_clk,
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o_O=rtio_half_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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@ -54,13 +66,15 @@ class _RTIOCRG(Module, AutoCSR):
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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p_CLKIN1_PERIOD=16.0, p_CLKIN2_PERIOD=16.0,
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i_CLKIN1=rtio_half_internal_clk,
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i_CLKIN2=rtio_half_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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# VCO @ 1GHz when using 62.5MHz input at the PLL
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# (125MHz on SMA)
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p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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