M-Labs
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artiq
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Globally update UART baudrate to 921600.

pull/668/head
whitequark 2017-01-24 22:25:58 +00:00
parent e5085c063f
commit b29e2d5bfe
8 changed files with 8 additions and 4 deletions
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1
artiq/firmware/runtime/lib.rs
View File

@ -57,7 +57,6 @@ mod moninj;
mod analyzer;
fn startup() {
board::uart::set_speed(921600);
board::clock::init();
info!("ARTIQ runtime starting...");
info!("software version {}", cfg!(git_describe));

2
artiq/frontend/artiq_devtool.py
View File

@ -100,7 +100,7 @@ def main():
logger.info("Booting runtime")
flterm = run_command(
"{env} python3 flterm.py {serial} " +
"{env} python3 flterm.py {serial} --speed 921600" +
"--kernel /tmp/{tmp}/runtime.bin " +
("--upload-only" if action == "boot" else "--output-only"))
artiq_flash = run_command(

1
artiq/gateware/targets/kc705_dds.py
View File

@ -112,6 +112,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
uart_baudrate=921600,
**kwargs)
AMPSoC.__init__(self)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):

1
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -33,6 +33,7 @@ class Master(MiniSoC, AMPSoC):
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
uart_baudrate=921600,
**kwargs)
AMPSoC.__init__(self)

1
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -131,6 +131,7 @@ class Satellite(BaseSoC):
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
uart_baudrate=921600,
**kwargs)
platform = self.platform

1
artiq/gateware/targets/phaser.py
View File

@ -169,6 +169,7 @@ class Phaser(MiniSoC, AMPSoC):
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
uart_baudrate=921600,
**kwargs)
AMPSoC.__init__(self)
self.platform.toolchain.bitstream_commands.extend([

1
artiq/gateware/targets/pipistrello.py
View File

@ -160,6 +160,7 @@ class Demo(BaseSoC, AMPSoC):
l2_size=64*1024,
ident=artiq_version,
clk_freq=75*1000*1000,
uart_baudrate=921600,
**kwargs)
AMPSoC.__init__(self)

4
doc/manual/installing_from_source.rst
View File

@ -187,7 +187,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
$ flterm /dev/ttyUSB1
$ flterm /dev/ttyUSB1 --speed 921600
MiSoC BIOS http://m-labs.hk
[...]
Booting from flash...
@ -197,7 +197,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
.. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
The communication parameters are 115200 8-N-1. Ensure that your user has access
The communication parameters are 921600 8-N-1. Ensure that your user has access
to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
.. _installing-the-host-side-software: