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https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
CSRConstant: also port DDS constants
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5db1f9794e
commit
7886827b80
@ -175,7 +175,7 @@ class NIST_QC1(_NIST_QCx):
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.add_constant("DDS_AD9858")
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self.config["DDS_AD9858"] = 1
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -219,8 +219,8 @@ class NIST_QC2(_NIST_QCx):
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 11
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self.add_constant("DDS_AD9914")
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self.add_constant("DDS_ONEHOT_SEL")
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self.config["DDS_AD9914"] = True
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self.config["DDS_ONEHOT_SEL"] = True
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -181,7 +181,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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self.add_constant("DDS_AD9858")
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self.config["DDS_AD9858"] = True
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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@ -20,10 +20,10 @@ static int dds_read(int addr)
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{
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int r;
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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#define DDS_READ_FLAG 128
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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#define DDS_READ_FLAG 256
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#endif
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dds_write(addr | DDS_READ_FLAG, 0);
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@ -8,12 +8,12 @@
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#define DURATION_WRITE (5 << CONFIG_RTIO_FINE_TS_WIDTH)
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#if defined DDS_AD9858
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#if defined CONFIG_DDS_AD9858
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/* Assume 8-bit bus */
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#define DURATION_INIT (7*DURATION_WRITE) /* not counting FUD */
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#define DURATION_PROGRAM (8*DURATION_WRITE) /* not counting FUD */
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#elif defined DDS_AD9914
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#elif defined CONFIG_DDS_AD9914
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/* Assume 16-bit bus */
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/* DAC calibration takes max. 1ms as per datasheet */
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#define DURATION_DAC_CAL (147000 << CONFIG_RTIO_FINE_TS_WIDTH)
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@ -46,7 +46,7 @@ void dds_init(long long int timestamp, int channel)
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#endif
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channel <<= 1;
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DDS_WRITE(DDS_GPIO, channel);
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#ifndef DDS_AD9914
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#ifndef CONFIG_DDS_AD9914
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/*
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* Resetting a AD9914 intermittently crashes it. It does not produce any
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* output until power-cycled.
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@ -58,7 +58,7 @@ void dds_init(long long int timestamp, int channel)
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DDS_WRITE(DDS_GPIO, channel);
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#endif
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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/*
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* 2GHz divider disable
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* SYNCLK disable
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@ -72,7 +72,7 @@ void dds_init(long long int timestamp, int channel)
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DDS_WRITE(DDS_FUD, 0);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
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DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
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DDS_WRITE(DDS_CFR2H, 0x0080); /* Enable profile mode */
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@ -105,14 +105,14 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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#endif
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DDS_WRITE(DDS_GPIO, channel_enc << 1);
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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DDS_WRITE(DDS_FTW0, ftw & 0xff);
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DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
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DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
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DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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DDS_WRITE(DDS_FTWL, ftw & 0xffff);
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DDS_WRITE(DDS_FTWH, (ftw >> 16) & 0xffff);
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#endif
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@ -122,10 +122,10 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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*/
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if(phase_mode == PHASE_MODE_CONTINUOUS) {
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/* Do not clear phase accumulator on FUD */
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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DDS_WRITE(DDS_CFR2, 0x00);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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/* Disable autoclear phase accumulator and enables OSK. */
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DDS_WRITE(DDS_CFR1L, 0x0108);
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#endif
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@ -134,10 +134,10 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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long long int fud_time;
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/* Clear phase accumulator on FUD */
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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DDS_WRITE(DDS_CFR2, 0x40);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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/* Enable autoclear phase accumulator and enables OSK. */
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DDS_WRITE(DDS_CFR1L, 0x2108);
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#endif
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@ -148,14 +148,14 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
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continuous_phase_comp[channel] = pow;
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}
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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DDS_WRITE(DDS_POW0, pow & 0xff);
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DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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DDS_WRITE(DDS_POW, pow);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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DDS_WRITE(DDS_ASF, amplitude);
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#endif
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DDS_WRITE(DDS_FUD, 0);
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@ -8,7 +8,7 @@
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/* Maximum number of commands in a batch */
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#define DDS_MAX_BATCH 16
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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#define DDS_CFR0 0x00
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#define DDS_CFR1 0x01
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#define DDS_CFR2 0x02
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@ -23,7 +23,7 @@
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#define DDS_GPIO 0x41
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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#define DDS_CFR1L 0x01
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#define DDS_CFR1H 0x03
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#define DDS_CFR2L 0x05
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@ -40,11 +40,11 @@
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#define DDS_GPIO 0x81
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#endif
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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#define DDS_POW_WIDTH 14
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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#define DDS_POW_WIDTH 16
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#endif
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@ -166,10 +166,10 @@ static void ddsr(char *addr)
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return;
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}
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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printf("0x%02x\n", brg_ddsread(addr2));
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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printf("0x%04x\n", brg_ddsread(addr2));
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#endif
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}
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@ -205,13 +205,13 @@ static void ddsftw(char *n, char *ftw)
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#endif
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brg_ddssel(n2);
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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brg_ddswrite(DDS_FTW0, ftw2 & 0xff);
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brg_ddswrite(DDS_FTW1, (ftw2 >> 8) & 0xff);
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brg_ddswrite(DDS_FTW2, (ftw2 >> 16) & 0xff);
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brg_ddswrite(DDS_FTW3, (ftw2 >> 24) & 0xff);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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brg_ddswrite(DDS_FTWL, ftw2 & 0xffff);
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brg_ddswrite(DDS_FTWH, (ftw2 >> 16) & 0xffff);
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#endif
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@ -224,7 +224,7 @@ static void ddsreset(void)
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brg_ddsreset();
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}
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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static void ddsinit(void)
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{
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brg_ddsreset();
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@ -236,7 +236,7 @@ static void ddsinit(void)
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}
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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static void ddsinit(void)
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{
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long long int t;
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@ -273,24 +273,24 @@ static void do_ddstest_one(unsigned int i)
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for(j=0; j<12; j++) {
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f = v[j];
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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brg_ddswrite(DDS_FTW0, f & 0xff);
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brg_ddswrite(DDS_FTW1, (f >> 8) & 0xff);
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brg_ddswrite(DDS_FTW2, (f >> 16) & 0xff);
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brg_ddswrite(DDS_FTW3, (f >> 24) & 0xff);
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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brg_ddswrite(DDS_FTWL, f & 0xffff);
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brg_ddswrite(DDS_FTWH, (f >> 16) & 0xffff);
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#endif
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brg_ddsfud();
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#ifdef DDS_AD9858
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#ifdef CONFIG_DDS_AD9858
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g = brg_ddsread(DDS_FTW0);
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g |= brg_ddsread(DDS_FTW1) << 8;
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g |= brg_ddsread(DDS_FTW2) << 16;
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g |= brg_ddsread(DDS_FTW3) << 24;
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#endif
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#ifdef DDS_AD9914
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#ifdef CONFIG_DDS_AD9914
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g = brg_ddsread(DDS_FTWL);
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g |= brg_ddsread(DDS_FTWH) << 16;
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#endif
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