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mirror of https://github.com/m-labs/artiq.git synced 2024-12-05 01:36:39 +08:00
artiq/artiq/gateware
2016-11-20 16:39:22 +01:00
..
amp gateware: rewrite mailbox to use bits_for. 2016-11-01 06:28:43 +00:00
dsp sawg: fix b delay width 2016-11-20 16:39:22 +01:00
rtio rtio: auto clear output event data and address 2016-11-19 16:12:27 +01:00
targets phaser: 150 MHz rtio/jesd clock 2016-11-19 13:16:30 +01:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9xxx.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc1.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
phaser.py phaser: spi, sma_gpio: 2.5 V 2016-10-27 15:53:49 +02:00
soc.py gateware: extend mailbox to 3 entries. 2016-10-21 12:09:14 +00:00
spi.py gateware/spi: fix import 2016-10-17 14:07:11 +08:00