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analyzer: use CRI and connect at RTIO core
This causes DMA events to be included in analyzer traces.
This commit is contained in:
parent
0b4922e0f4
commit
d2f2415b50
@ -3,6 +3,7 @@ from migen.genlib.record import Record, layout_len
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from artiq.gateware.rtio.cri import commands as cri_commands
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from artiq.coredevice.comm_analyzer import MessageType, ExceptionType
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@ -42,7 +43,7 @@ assert layout_len(stopped_layout) == message_len
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class MessageEncoder(Module, AutoCSR):
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def __init__(self, kcsrs, rtio_counter, enable):
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def __init__(self, cri, enable):
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self.source = stream.Endpoint([("data", message_len)])
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self.overflow = CSRStatus()
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@ -52,36 +53,34 @@ class MessageEncoder(Module, AutoCSR):
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input_output_stb = Signal()
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input_output = Record(input_output_layout)
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o_data = kcsrs.o_data.storage
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o_address = kcsrs.o_address.storage
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i_data = kcsrs.i_data.status
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self.comb += [
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input_output.channel.eq(kcsrs.chan_sel.storage),
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input_output.address_padding.eq(o_address),
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input_output.rtio_counter.eq(rtio_counter),
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If(kcsrs.o_we.re,
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input_output.channel.eq(cri.chan_sel),
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input_output.address_padding.eq(cri.o_address),
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input_output.rtio_counter.eq(cri.counter),
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If(cri.cmd == cri_commands["write"],
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input_output.message_type.eq(MessageType.output.value),
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input_output.timestamp.eq(kcsrs.o_timestamp.storage),
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input_output.data.eq(o_data)
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input_output.timestamp.eq(cri.o_timestamp),
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input_output.data.eq(cri.o_data)
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).Else(
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input_output.message_type.eq(MessageType.input.value),
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input_output.timestamp.eq(kcsrs.i_timestamp.status),
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input_output.data.eq(i_data)
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input_output.timestamp.eq(cri.i_timestamp),
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input_output.data.eq(cri.i_data)
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),
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input_output_stb.eq(kcsrs.o_we.re | kcsrs.i_re.re)
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input_output_stb.eq((cri.cmd == cri_commands["write"]) |
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(cri.cmd == cri_commands["read"]))
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]
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exception_stb = Signal()
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exception = Record(exception_layout)
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self.comb += [
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exception.message_type.eq(MessageType.exception.value),
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exception.channel.eq(kcsrs.chan_sel.storage),
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exception.rtio_counter.eq(rtio_counter),
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exception.channel.eq(cri.chan_sel),
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exception.rtio_counter.eq(cri.counter),
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]
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for ename in ("o_underflow_reset", "o_sequence_error_reset",
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"o_collision_reset", "i_overflow_reset"):
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self.comb += \
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If(getattr(kcsrs, ename).re,
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If(cri.cmd == cri_commands[ename],
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exception_stb.eq(1),
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exception.exception_type.eq(
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getattr(ExceptionType, ename).value)
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@ -90,7 +89,7 @@ class MessageEncoder(Module, AutoCSR):
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stopped = Record(stopped_layout)
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self.comb += [
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stopped.message_type.eq(MessageType.stopped.value),
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stopped.rtio_counter.eq(rtio_counter),
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stopped.rtio_counter.eq(cri.counter),
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]
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enable_r = Signal()
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@ -180,13 +179,13 @@ class DMAWriter(Module, AutoCSR):
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class Analyzer(Module, AutoCSR):
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def __init__(self, kcsrs, rtio_counter, membus, fifo_depth=128):
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def __init__(self, cri, membus, fifo_depth=128):
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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self.submodules.message_encoder = MessageEncoder(
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kcsrs, rtio_counter, self.enable.storage)
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cri, self.enable.storage)
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self.submodules.fifo = stream.SyncFIFO(
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[("data", message_len)], fifo_depth, True)
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self.submodules.converter = stream.Converter(
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@ -159,8 +159,8 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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@ -241,8 +241,8 @@ class Phaser(MiniSoC, AMPSoC):
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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platform.add_false_path_constraints(
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@ -218,8 +218,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.register_kernel_cpu_csrdevice("rtio")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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