mirror of https://github.com/m-labs/artiq.git
drtio: integrate aux controller
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@ -2,7 +2,7 @@ from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller
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from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller, aux_controller
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class DRTIOSatellite(Module):
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@ -44,6 +44,12 @@ class DRTIOSatellite(Module):
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self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
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]
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return self.aux_controller.get_csrs()
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class DRTIOMaster(Module):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
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@ -58,10 +64,14 @@ class DRTIOMaster(Module):
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self.rt_packets, channel_count, fine_ts_width)
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self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_kernel_csrs(self):
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return self.rt_controller.get_kernel_csrs()
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs())
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self.rt_manager.get_csrs() +
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self.aux_controller.get_csrs())
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