mirror of https://github.com/m-labs/artiq.git
rtio/sed/OutputDriver: support channels with different fine timestamp widths
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@ -61,6 +61,8 @@ class OutputDriver(Module):
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# demultiplex channels (adds one pipeline stage)
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for n, channel in enumerate(channels):
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oif = channel.interface.o
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onehot_stb = []
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onehot_fine_ts = []
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onehot_address = []
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@ -69,14 +71,14 @@ class OutputDriver(Module):
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selected = Signal()
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self.comb += selected.eq(lane_data.valid & ~lane_data.collision & (lane_data.payload.channel == n))
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onehot_stb.append(selected)
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if hasattr(lane_data.payload, "fine_ts"):
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onehot_fine_ts.append(Mux(selected, lane_data.payload.fine_ts, 0))
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if hasattr(lane_data.payload, "fine_ts") and hasattr(oif, "fine_ts"):
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ts_shift = len(lane_data.payload.fine_ts) - len(oif.fine_ts)
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onehot_fine_ts.append(Mux(selected, lane_data.payload.fine_ts[ts_shift:], 0))
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if hasattr(lane_data.payload, "address"):
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onehot_address.append(Mux(selected, lane_data.payload.address, 0))
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if hasattr(lane_data.payload, "data"):
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onehot_data.append(Mux(selected, lane_data.payload.data, 0))
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oif = channel.interface.o
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self.sync += oif.stb.eq(reduce(or_, onehot_stb))
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if hasattr(oif, "fine_ts"):
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self.sync += oif.fine_ts.eq(reduce(or_, onehot_fine_ts))
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