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artiq
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ad9xxx -> ad9_dds

This commit is contained in:
Sebastien Bourdeauducq 2017-01-04 11:34:52 +01:00
parent 52fda27cb5
commit 86f6b391b7
2 changed files with 8 additions and 8 deletions
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6
artiq/gateware/ad9xxx.py → artiq/gateware/ad9_dds.py
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@ -4,7 +4,7 @@ from migen.genlib.misc import WaitTimer
from misoc.interconnect import wishbone
class AD9xxx(Module):
class AD9_DDS(Module):
"""Wishbone interface to the AD9858 and AD9914 DDS chips.
Addresses 0-2**len(pads.a)-1 map the AD9xxx registers.
@ -178,5 +178,5 @@ class _TestPads:
if __name__ == "__main__":
pads = _TestPads()
dut = AD9xxx(pads)
run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9xxx.vcd")
dut = AD9_DDS(pads)
run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9_dds.vcd")

10
artiq/gateware/rtio/phy/dds.py
View File

@ -1,13 +1,13 @@
from migen import *
from artiq.gateware import ad9xxx
from artiq.gateware import ad9_dds
from artiq.gateware.rtio.phy.wishbone import RT2WB
class _AD9xxx(Module):
class _AD9_DDS(Module):
def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
ad9xxx.AD9xxx(pads, **kwargs))
ad9_dds.AD9_DDS(pads, **kwargs))
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
self.rtlink = self._rt2wb.rtlink
self.probes = [Signal(32) for i in range(nchannels)]
@ -56,6 +56,6 @@ class _AD9xxx(Module):
for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
class AD9914(_AD9xxx):
class AD9914(_AD9_DDS):
def __init__(self, *args, **kwargs):
_AD9xxx.__init__(self, 0x2d, *args, **kwargs)
_AD9_DDS.__init__(self, 0x2d, *args, **kwargs)