mirror of https://github.com/m-labs/artiq.git
rtio: add input-only channel
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parent
279f0d568d
commit
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@ -31,6 +31,32 @@ class _OSERDESE2_8X(Module):
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o_O=pad, o_OB=pad_n)
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class _ISERDESE2_8X(Module):
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def __init__(self, pad, pad_n=None):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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# # #
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pad_i = Signal()
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i = self.i
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self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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p_DATA_WIDTH=8,
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p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
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o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
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i_D=pad_i,
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i_CLK=ClockSignal("rtiox4"),
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i_CLKB=~ClockSignal("rtiox4"),
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i_CE1=1, i_RST=0,
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i_CLKDIV=ClockSignal("rio_phy"))
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if pad_n is None:
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self.comb += pad_i.eq(pad)
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else:
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self.specials += Instance("IBUFDS", o_O=pad_i, i_I=pad, i_IB=pad_n)
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class _IOSERDESE2_8X(Module):
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def __init__(self, pad, pad_n=None):
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self.o = Signal(8)
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@ -80,3 +106,9 @@ class Inout_8X(ttl_serdes_generic.Inout):
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serdes = _IOSERDESE2_8X(pad, pad_n)
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self.submodules += serdes
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ttl_serdes_generic.Inout.__init__(self, serdes)
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class Input_8X(ttl_serdes_generic.Inout):
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def __init__(self, pad, pad_n=None):
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serdes = _ISERDESE2_8X(pad, pad_n)
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self.submodules += serdes
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ttl_serdes_generic.Inout.__init__(self, serdes)
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