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soc: factor timer, kernel CPU and mailbox

This commit is contained in:
Sebastien Bourdeauducq 2015-05-01 18:51:24 +08:00
parent 1684586ae8
commit 62669f9ff2
4 changed files with 48 additions and 37 deletions
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4
artiq/frontend/artiq_flash.sh
View File

@ -90,7 +90,7 @@ fi
if [ "$BOARD" == "kc705" ]
then
UDEV_RULES=99-kc705.rules
BITSTREAM=artiq_kc705-top-kc705.bit
BITSTREAM=artiq_kc705-nist_qc1-kc705.bit
CABLE=jtaghs1_fast
PROXY=bscan_spi_kc705.bit
BIOS_ADDR=0xaf0000
@ -100,7 +100,7 @@ then
elif [ "$BOARD" == "pipistrello" ]
then
UDEV_RULES=99-papilio.rules
BITSTREAM=artiq_pipistrello-top-pipistrello.bin
BITSTREAM=artiq_pipistrello-nist_qc1-pipistrello.bin
CABLE=papilio
PROXY=bscan_spi_lx45_csg324.bit
BIOS_ADDR=0x170000

30
artiq/gateware/soc.py Normal file
View File

@ -0,0 +1,30 @@
from misoclib.soc import mem_decoder
from misoclib.cpu.peripherals import timer
from artiq.gateware import amp
class AMPSoC:
"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs.
Users must disable the timer from the platform SoC and provide
a "mailbox" entry in the memory map.
"""
def __init__(self):
if not hasattr(self, "cpu_or_bridge"):
raise ValueError("Platform SoC must be initialized first")
if hasattr(self, "timer0"):
raise ValueError("Timer already exists. "
"Initialize platform SoC using with_timer=False")
self.submodules.timer0 = timer.Timer(width=64)
self.submodules.kernel_cpu = amp.KernelCPU(
self.platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)
self.add_memory_region("mailbox",
self.mem_map["mailbox"] | 0x80000000, 4)

25
soc/targets/artiq_kc705.py
View File

@ -9,7 +9,8 @@ from misoclib.soc import mem_decoder
from misoclib.cpu.peripherals import timer
from targets.kc705 import MiniSoC
from artiq.gateware import amp, rtio, ad9858, nist_qc1
from artiq.gateware.soc import AMPSoC
from artiq.gateware import rtio, ad9858, nist_qc1
from artiq.gateware.rtio.phy import ttl_simple
@ -31,7 +32,7 @@ class _RTIOCRG(Module, AutoCSR):
o_O=self.cd_rtio.clk)
class Top(MiniSoC):
class NIST_QC1(MiniSoC, AMPSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtiocrg": 13,
@ -48,7 +49,7 @@ class Top(MiniSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self, platform,
cpu_type=cpu_type, with_timer=False, **kwargs)
self.submodules.timer0 = timer.Timer(width=64)
AMPSoC.__init__(self)
platform.add_extension(nist_qc1.fmc_adapter_io)
self.submodules.leds = gpio.GPIOOut(Cat(
@ -98,27 +99,17 @@ set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
# Kernel CPU
self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)
self.add_memory_region("mailbox",
self.mem_map["mailbox"] + 0x80000000, 4)
# CPU connections
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
self.add_memory_region("dds", self.mem_map["dds"] | 0x80000000, 64*4)
default_subtarget = Top
default_subtarget = NIST_QC1

26
soc/targets/artiq_pipistrello.py
View File

@ -4,10 +4,10 @@ from migen.bank import wbgen
from misoclib.com import gpio
from misoclib.soc import mem_decoder
from misoclib.cpu.peripherals import timer
from targets.pipistrello import BaseSoC
from artiq.gateware import amp, rtio, ad9858, nist_qc1
from artiq.gateware.soc import AMPSoC
from artiq.gateware import rtio, ad9858, nist_qc1
from artiq.gateware.rtio.phy import ttl_simple
@ -52,7 +52,7 @@ TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
class Top(BaseSoC):
class NIST_QC1(BaseSoC, AMPSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtiocrg": 13,
@ -69,7 +69,7 @@ class Top(BaseSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, with_timer=False, **kwargs)
self.submodules.timer0 = timer.Timer(width=64)
AMPSoC.__init__(self)
platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
"""
@ -125,27 +125,17 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.submodules.dds = ad9858.AD9858(dds_pads)
self.comb += dds_pads.fud_n.eq(~fud)
# Kernel CPU
self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)
self.add_memory_region("mailbox",
self.mem_map["mailbox"] + 0x80000000, 4)
# CPU connections
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
self.add_memory_region("dds", self.mem_map["dds"] | 0x80000000, 64*4)
default_subtarget = Top
default_subtarget = NIST_QC1