e4b16428f5
wrpll: fix run signal
2020-07-27 13:02:02 +08:00
8dd9a6d024
wrpll: fix scl signal
2020-07-27 12:59:32 +08:00
Sebastien Bourdeauducq
4340a5cfc1
rtio/dma: fix previous commit
2020-07-12 10:14:22 +08:00
Sebastien Bourdeauducq
f2e0d27334
rtio/dma: remove dead/broken code
2020-07-12 10:13:18 +08:00
Sebastien Bourdeauducq
901be75ba4
sayma_rtm: fix Si5324 reset
...
Closes #1483
2020-07-11 09:51:01 +08:00
Sebastien Bourdeauducq
2d1f1fff7f
kasli_generic: do not attempt to use SFP LED for RTIO on 2.0+
2020-07-08 18:14:44 +08:00
Sebastien Bourdeauducq
cb76f9da89
metlino: fix CSR collisions
...
Closes #1425
2020-05-29 15:59:44 +08:00
Sebastien Bourdeauducq
bd9eec15c0
metlino: increase number of DRTIO links
...
Seems OK with Vivado 2019.2.
2020-05-29 15:59:16 +08:00
Sebastien Bourdeauducq
d8b5bcf019
sayma_amc: support uTCA backplane for DRTIO
2020-05-29 14:58:49 +08:00
Sebastien Bourdeauducq
8b939b7cb3
sayma_amc: remove Master (obsoleted by Metlino)
2020-05-29 14:40:49 +08:00
Sebastien Bourdeauducq
4e9a529e5a
kasli: integrate WRPLL
2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq
60e5f1c18e
kasli: DRTIO support for Kasli 2
2020-05-07 20:09:43 +08:00
Sebastien Bourdeauducq
1f2182d4c7
kasli: default to hardware v2
2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq
b83afedf43
kasli: light up ERROR LED on panic
2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq
7e400a78f4
kasli: compile tester for hw 2.0 by default
2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq
3a7819704a
rtio: support direct 64-bit now CSR in KernelInitiator
2020-04-26 16:04:32 +08:00
Sebastien Bourdeauducq
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
Robert Jördens
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
Sebastien Bourdeauducq
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
Sebastien Bourdeauducq
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
Sebastien Bourdeauducq
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
Sebastien Bourdeauducq
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
Robert Jördens
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
Sebastien Bourdeauducq
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
Sebastien Bourdeauducq
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
Sebastien Bourdeauducq
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
Sebastien Bourdeauducq
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
Robert Jördens
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
Robert Jördens
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
Robert Jördens
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
Sebastien Bourdeauducq
6c3e71a83a
wrpll: cleanup
2020-01-18 09:43:43 +08:00
Sebastien Bourdeauducq
344f8bd12a
wrpll: collector patch from Weida
2020-01-18 09:42:58 +08:00
Sebastien Bourdeauducq
6c948c7726
sayma: RF switch control is active-low on Basemod, invert
2020-01-16 08:59:52 +08:00
Sebastien Bourdeauducq
50302d57c0
wrpll: more careful I2C timing
2020-01-14 20:03:46 +08:00
Sebastien Bourdeauducq
105dd60c78
wrpll: ADPLLProgrammer mini test bench and fixes
2020-01-14 16:52:25 +08:00
Sebastien Bourdeauducq
3242e9ec6c
wrpll: loop test
2020-01-13 22:31:57 +08:00
Sebastien Bourdeauducq
8ec0f2e717
wrpll: implement ADPLLProgrammer
2020-01-13 22:30:11 +08:00
Sebastien Bourdeauducq
d685619bcd
wrpll: collector code modifications from Weida
2020-01-13 20:42:41 +08:00
Sebastien Bourdeauducq
a666766f38
wrpll: add ADPLL offset registers
2019-12-30 22:19:42 +08:00
Sebastien Bourdeauducq
5c6e394928
ddmtd: add collector
2019-12-30 22:17:44 +08:00
Sebastien Bourdeauducq
f57f235dca
wrpll: new frequency meter
...
As per Mattermost discussion with Tom.
2019-12-30 19:47:57 +08:00
Sebastien Bourdeauducq
9e15ff7e6a
wrpll: improve DDMTD deglitcher
2019-12-30 16:56:06 +08:00
Sebastien Bourdeauducq
b7f1623197
sayma_rtm: connect attenuator shift registers in series
2019-12-20 18:58:31 +08:00
Sebastien Bourdeauducq
1c9cbe6285
sayma_rtm: add basemod attenuators on RTIO
2019-12-20 15:25:55 +08:00
Sebastien Bourdeauducq
6ee15fbcae
sayma_rtm: basemod RF switches
2019-12-18 10:33:29 +08:00
Sebastien Bourdeauducq
52112d54f9
kasli_generic: expose peripheral_processors dictionary. Closes #1403
2019-12-10 10:30:06 +08:00
Sebastien Bourdeauducq
150a02117c
sayma_rtm: drive clk_src_ext_sel
2019-12-09 19:47:50 +08:00
Sebastien Bourdeauducq
307a6ca140
gth_ultrascale: make OBUFDS_GTE3 work
...
https://www.xilinx.com/support/answers/67919.html
2019-12-09 18:13:22 +08:00
Sebastien Bourdeauducq
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
Sebastien Bourdeauducq
05e2e1899a
wrpll: update OBUFDS_GTE2 comment
...
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
2019-12-09 11:58:54 +08:00
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