mirror of https://github.com/m-labs/artiq.git
drtio: introduce 'standard request' interface in RT packet layer
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parent
2b8729f326
commit
6b7c781ff2
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@ -100,13 +100,13 @@ class RTController(Module):
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fifo_spaces.adr.eq(chan_sel),
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last_timestamps.adr.eq(chan_sel),
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last_timestamps.dat_w.eq(self.cri.timestamp),
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rt_packets.write_channel.eq(chan_sel),
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rt_packets.write_address.eq(self.cri.o_address),
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rt_packets.write_data.eq(self.cri.o_data),
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rt_packets.sr_channel.eq(chan_sel),
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rt_packets.sr_address.eq(self.cri.o_address),
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rt_packets.sr_data.eq(self.cri.o_data),
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rt_packets.sr_timestamp.eq(self.cri.timestamp),
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If(rt_packets_fifo_request,
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rt_packets.write_timestamp.eq(0xffff000000000000)
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).Else(
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rt_packets.write_timestamp.eq(self.cri.timestamp)
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rt_packets.sr_notwrite.eq(1),
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rt_packets.sr_address.eq(0)
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)
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]
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@ -159,8 +159,8 @@ class RTController(Module):
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)
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fsm.act("WRITE",
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status_wait.eq(1),
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rt_packets.write_stb.eq(1),
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If(rt_packets.write_ack,
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rt_packets.sr_stb.eq(1),
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If(rt_packets.sr_ack,
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fifo_spaces.we.eq(1),
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fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1),
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last_timestamps.we.eq(1),
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@ -174,9 +174,9 @@ class RTController(Module):
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fsm.act("GET_FIFO_SPACE",
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status_wait.eq(1),
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rt_packets_fifo_request.eq(1),
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rt_packets.write_stb.eq(1),
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rt_packets.sr_stb.eq(1),
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rt_packets.fifo_space_not_ack.eq(1),
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If(rt_packets.write_ack,
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If(rt_packets.sr_ack,
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NextState("GET_FIFO_SPACE_REPLY")
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)
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)
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@ -211,7 +211,7 @@ class RTController(Module):
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)
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]
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self.sync += \
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If((rt_packets.write_stb & rt_packets.write_ack & rt_packets_fifo_request),
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If((rt_packets.sr_stb & rt_packets.sr_ack & rt_packets_fifo_request),
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self.csrs.o_dbg_fifo_space_req_cnt.status.eq(
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self.csrs.o_dbg_fifo_space_req_cnt.status + 1)
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)
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@ -61,20 +61,28 @@ class _CrossDomainNotification(Module):
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class RTPacketMaster(Module):
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def __init__(self, link_layer, write_fifo_depth=4):
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def __init__(self, link_layer, sr_fifo_depth=4):
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# all interface signals in sys domain unless otherwise specified
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# write interface, optimized for throughput
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self.write_stb = Signal()
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self.write_ack = Signal()
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(512)
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# standard request interface
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#
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# notwrite=1 address=0 FIFO space request <channel>
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# notwrite=1 address=1 read request <channel, timestamp>
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# notwrite=1 address=2 read consume
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#
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# optimized for write throughput
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# requests are performed on the DRTIO link preserving their order of issue
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# this is important for FIFO space requests, which have to be ordered
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# wrt writes.
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self.sr_stb = Signal()
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self.sr_ack = Signal()
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self.sr_notwrite = Signal()
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self.sr_timestamp = Signal(64)
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self.sr_channel = Signal(16)
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self.sr_address = Signal(16)
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self.sr_data = Signal(512)
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# fifo space interface
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# write with timestamp[48:] == 0xffff to make a fifo space request
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# (space requests have to be ordered wrt writes)
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# fifo space reply interface
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self.fifo_space_not = Signal()
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self.fifo_space_not_ack = Signal()
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self.fifo_space = Signal(16)
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@ -122,63 +130,66 @@ class RTPacketMaster(Module):
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self.submodules += rx_dp
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# Write FIFO and extra data count
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wfifo = ClockDomainsRenamer({"write": "sys_with_rst", "read": "rtio_with_rst"})(
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AsyncFIFO(64+16+16+512, write_fifo_depth))
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self.submodules += wfifo
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write_timestamp_d = Signal(64)
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write_channel_d = Signal(16)
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write_address_d = Signal(16)
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write_data_d = Signal(512)
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sr_fifo = ClockDomainsRenamer({"write": "sys_with_rst", "read": "rtio_with_rst"})(
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AsyncFIFO(1+64+16+16+512, sr_fifo_depth))
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self.submodules += sr_fifo
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sr_notwrite_d = Signal()
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sr_timestamp_d = Signal(64)
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sr_channel_d = Signal(16)
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sr_address_d = Signal(16)
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sr_data_d = Signal(512)
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self.comb += [
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wfifo.we.eq(self.write_stb),
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self.write_ack.eq(wfifo.writable),
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wfifo.din.eq(Cat(self.write_timestamp, self.write_channel,
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self.write_address, self.write_data)),
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Cat(write_timestamp_d, write_channel_d,
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write_address_d, write_data_d).eq(wfifo.dout)
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sr_fifo.we.eq(self.sr_stb),
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self.sr_ack.eq(sr_fifo.writable),
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sr_fifo.din.eq(Cat(self.sr_notwrite, self.sr_timestamp, self.sr_channel,
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self.sr_address, self.sr_data)),
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Cat(sr_notwrite_d, sr_timestamp_d, sr_channel_d,
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sr_address_d, sr_data_d).eq(sr_fifo.dout)
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]
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wfb_readable = Signal()
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wfb_re = Signal()
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sr_buf_readable = Signal()
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sr_buf_re = Signal()
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self.comb += wfifo.re.eq(wfifo.readable & (~wfb_readable | wfb_re))
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self.comb += sr_fifo.re.eq(sr_fifo.readable & (~sr_buf_readable | sr_buf_re))
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self.sync.rtio += \
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If(wfifo.re,
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wfb_readable.eq(1),
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).Elif(wfb_re,
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wfb_readable.eq(0),
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If(sr_fifo.re,
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sr_buf_readable.eq(1),
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).Elif(sr_buf_re,
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sr_buf_readable.eq(0),
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)
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write_timestamp = Signal(64)
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write_channel = Signal(16)
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write_address = Signal(16)
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write_extra_data_cnt = Signal(8)
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write_data = Signal(512)
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sr_notwrite = Signal()
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sr_timestamp = Signal(64)
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sr_channel = Signal(16)
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sr_address = Signal(16)
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sr_extra_data_cnt = Signal(8)
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sr_data = Signal(512)
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self.sync.rtio += If(wfifo.re,
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write_timestamp.eq(write_timestamp_d),
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write_channel.eq(write_channel_d),
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write_address.eq(write_address_d),
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write_data.eq(write_data_d))
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self.sync.rtio += If(sr_fifo.re,
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sr_notwrite.eq(sr_notwrite_d),
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sr_timestamp.eq(sr_timestamp_d),
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sr_channel.eq(sr_channel_d),
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sr_address.eq(sr_address_d),
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sr_data.eq(sr_data_d))
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short_data_len = tx_plm.field_length("write", "short_data")
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write_extra_data_d = Signal(512)
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self.comb += write_extra_data_d.eq(write_data_d[short_data_len:])
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sr_extra_data_d = Signal(512)
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self.comb += sr_extra_data_d.eq(sr_data_d[short_data_len:])
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for i in range(512//ws):
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self.sync.rtio += If(wfifo.re,
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If(write_extra_data_d[ws*i:ws*(i+1)] != 0, write_extra_data_cnt.eq(i+1)))
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self.sync.rtio += If(sr_fifo.re,
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If(sr_extra_data_d[ws*i:ws*(i+1)] != 0, sr_extra_data_cnt.eq(i+1)))
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write_extra_data = Signal(512)
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self.sync.rtio += If(wfifo.re, write_extra_data.eq(write_extra_data_d))
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sr_extra_data = Signal(512)
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self.sync.rtio += If(sr_fifo.re, sr_extra_data.eq(sr_extra_data_d))
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extra_data_ce = Signal()
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extra_data_last = Signal()
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extra_data_counter = Signal(max=512//ws+1)
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self.comb += [
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Case(extra_data_counter,
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{i+1: tx_dp.raw_data.eq(write_extra_data[i*ws:(i+1)*ws])
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{i+1: tx_dp.raw_data.eq(sr_extra_data[i*ws:(i+1)*ws])
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for i in range(512//ws)}),
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extra_data_last.eq(extra_data_counter == write_extra_data_cnt)
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extra_data_last.eq(extra_data_counter == sr_extra_data_cnt)
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]
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self.sync.rtio += \
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If(extra_data_ce,
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@ -230,8 +241,9 @@ class RTPacketMaster(Module):
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
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tx_fsm.act("IDLE",
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If(wfb_readable,
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If(write_timestamp[48:] == 0xffff,
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If(sr_buf_readable,
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If(sr_notwrite,
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# TODO: sr_address
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NextState("FIFO_SPACE")
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).Else(
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NextState("WRITE")
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@ -250,14 +262,14 @@ class RTPacketMaster(Module):
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)
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tx_fsm.act("WRITE",
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tx_dp.send("write",
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timestamp=write_timestamp,
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channel=write_channel,
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address=write_address,
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extra_data_cnt=write_extra_data_cnt,
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short_data=write_data[:short_data_len]),
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timestamp=sr_timestamp,
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channel=sr_channel,
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address=sr_address,
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extra_data_cnt=sr_extra_data_cnt,
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short_data=sr_data[:short_data_len]),
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If(tx_dp.packet_last,
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If(write_extra_data_cnt == 0,
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wfb_re.eq(1),
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If(sr_extra_data_cnt == 0,
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sr_buf_re.eq(1),
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NextState("IDLE")
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).Else(
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NextState("WRITE_EXTRA")
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@ -268,14 +280,14 @@ class RTPacketMaster(Module):
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tx_dp.raw_stb.eq(1),
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extra_data_ce.eq(1),
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If(extra_data_last,
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wfb_re.eq(1),
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sr_buf_re.eq(1),
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NextState("IDLE")
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)
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)
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tx_fsm.act("FIFO_SPACE",
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tx_dp.send("fifo_space_request", channel=write_channel),
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tx_dp.send("fifo_space_request", channel=sr_channel),
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If(tx_dp.packet_last,
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wfb_re.eq(1),
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sr_buf_re.eq(1),
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NextState("IDLE")
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)
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)
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