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gateware/targets/phaser: jesd core now handles jsync completely

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This commit is contained in:
Florent Kermarrec 2017-04-26 22:23:59 +02:00
parent 8ebb33c05c
commit 79c339d4ac
2 changed files with 3 additions and 12 deletions
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2
artiq/firmware/libboard/ad9154.rs
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@ -67,7 +67,7 @@ fn jesd_stpl(en: bool) {
fn jesd_jsync() -> bool {
unsafe {
csr::ad9154::jesd_jsync_read() != 0
csr::ad9154::jesd_control_jsync_read() != 0
}
}

13
artiq/gateware/targets/phaser.py
View File

@ -5,7 +5,6 @@ import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from migen.genlib.io import DifferentialInput
from jesd204b.common import (JESD204BTransportSettings,
JESD204BPhysicalSettings,
@ -78,7 +77,6 @@ class _PhaserCRG(Module, AutoCSR):
class AD9154JESD(Module, AutoCSR):
def __init__(self, platform):
self.jreset = CSRStorage(reset=1)
self.jsync = CSRStatus()
ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
@ -115,19 +113,12 @@ class AD9154JESD(Module, AutoCSR):
self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
converter_data_width=32))
self.submodules.control = to_jesd(JESD204BCoreTXControl(self.core))
sync_pads = platform.request("ad9154_sync")
jsync = Signal()
self.specials += [
DifferentialInput(sync_pads.p, sync_pads.n, jsync),
MultiReg(jsync, self.jsync.status)
]
self.core.register_jsync(platform.request("ad9154_sync"))
self.comb += [
platform.request("ad9154_txen", 0).eq(1),
platform.request("ad9154_txen", 1).eq(1),
self.core.jsync.eq(jsync),
platform.request("user_led", 3).eq(jsync),
platform.request("user_led", 3).eq(self.core.jsync),
]
# blinking leds for transceiver reset status