mirror of https://github.com/m-labs/artiq.git
rtio: use large data register
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@ -61,7 +61,7 @@ class KernelInitiator(Module, AutoCSR):
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self.reset_phy = CSR()
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self.chan_sel = CSRStorage(24)
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self.o_data = CSRStorage(32, write_from_dev=True) # XXX -> 512
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self.o_data = CSRStorage(512, write_from_dev=True)
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self.o_address = CSRStorage(16)
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self.o_timestamp = CSRStorage(64)
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self.o_we = CSR()
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