mirror of https://github.com/m-labs/artiq.git
rtio: auto clear output event data and address
This is to support channels where variable length event data is well-defined through zero-padding. E.g. in the case of `Spline` zero-padding of events naturally corresponds to low-order knots. Use timestamp change as trigger. This assumes that writes to the timestamp register always precede address and data writes. It does not break support for ganged writes of the same event timestamp and data/address to multiple channels or channel-addresses.
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@ -334,9 +334,9 @@ class _KernelCSRs(AutoCSR):
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self.chan_sel = CSRStorage(chan_sel_width)
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if data_width:
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self.o_data = CSRStorage(data_width)
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self.o_data = CSRStorage(data_width, write_from_dev=True)
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if address_width:
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self.o_address = CSRStorage(address_width)
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self.o_address = CSRStorage(address_width, write_from_dev=True)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_we = CSR()
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self.o_status = CSRStatus(5)
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@ -498,5 +498,13 @@ class RTIO(Module):
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<< fine_ts_width)
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)
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# Auto clear/zero pad event data
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self.comb += [
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self.kcsrs.o_data.dat_w.eq(0),
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self.kcsrs.o_data.we.eq(self.kcsrs.o_timestamp.re),
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self.kcsrs.o_address.dat_w.eq(0),
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self.kcsrs.o_address.we.eq(self.kcsrs.o_timestamp.re),
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]
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def get_csrs(self):
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return self.kcsrs.get_csrs()
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