mirror of https://github.com/m-labs/artiq.git
sawg: wir up limiting, saturating addition
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e53d0bcd5b
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@ -104,10 +104,11 @@ class Config(Module):
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def __init__(self, width):
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self.clr = Signal(4, reset=0b1111)
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self.iq_en = Signal(2, reset=0b01)
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self.limit = [[Signal((width, True), reset=-(1 << width - 1)),
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self.limits = [[Signal((width, True), reset=-(1 << width - 1)),
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Signal((width, True), reset=(1 << width - 1) - 1)]
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for i in range(2)]
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self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limit))),
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for i in range(3)]
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self.clipped = [Signal(2) for i in range(3)] # TODO
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self.i = Endpoint([("addr", bits_for(4 + len(self.limits))),
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("data", 16)])
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self.ce = Signal()
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@ -118,7 +119,7 @@ class Config(Module):
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pad = Signal()
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reg = Array([Cat(div, n), self.clr, self.iq_en, pad] +
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sum(self.limit, []))
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[Cat(*l) for l in self.limits])
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self.comb += [
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self.i.ack.eq(1),
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@ -161,7 +162,7 @@ class Channel(Module, SatAddMixin):
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self.widths = widths
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self.orders = orders
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self.parallelism = parallelism
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self.latency = a1.latency + b.latency + 1
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self.latency = a1.latency + b.latency + 2
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self.cordic_gain = a1.gain*b.gain
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###
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@ -172,17 +173,22 @@ class Channel(Module, SatAddMixin):
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b.ce.eq(cfg.ce),
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u.o.ack.eq(cfg.ce),
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Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
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b.i.x.eq(self.sat_add([a1.xo[0], a2.xo[0]])),
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b.i.y.eq(self.sat_add([a1.yo[0], a2.yo[0]])),
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]
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self.sync += [
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b.i.x.eq(self.sat_add(a1.xo[0], a2.xo[0],
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limits=cfg.limits[0],
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clipped=cfg.clipped[0])),
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b.i.y.eq(self.sat_add(a1.yo[0], a2.yo[0],
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limits=cfg.limits[1],
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clipped=cfg.clipped[1])),
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eqh(du.i, u.o.a0),
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]
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# wire up outputs and q_{i,o} exchange
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for o, x, y in zip(self.o, b.xo, self.y_in):
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self.sync += [
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o.eq(self.sat_add([
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du.o,
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Mux(cfg.iq_en[0], x, 0),
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Mux(cfg.iq_en[1], y, 0)])),
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o.eq(self.sat_add(
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du.o, Mux(cfg.iq_en[0], x, 0), Mux(cfg.iq_en[1], y, 0),
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limits=cfg.limits[2], clipped=cfg.clipped[2])),
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]
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def connect_y(self, buddy):
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