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rtio: fix indentation

This commit is contained in:
Sebastien Bourdeauducq 2017-04-06 12:08:13 +08:00
parent 207453efcd
commit c0100ebc56
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/rtio/core.py
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@ -90,8 +90,8 @@ class _OutputManager(Module):
# Note: replace may be asserted at the same time as collision
# when addresses are different. In that case, it is a collision.
self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
# Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors.
# Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors.
self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
buf.timestamp[fine_ts_width:])
if interface.enable_replace: