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gateware: add moninj to drtio targets
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a12876b239
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@ -99,6 +99,11 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
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self.csr_devices.append("rtio_core")
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@ -44,6 +44,9 @@ class Satellite(BaseSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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if cfg == "simple_gbe":
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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