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artiq
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rtio: make 63-bit timestamp counter the default [soc]

This commit is contained in:
Sebastien Bourdeauducq 2015-03-12 13:10:35 +01:00
parent d38014b07d
commit 3122623c6f
2 changed files with 2 additions and 1 deletions
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2
artiq/gateware/rtio/core.py
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@ -294,7 +294,7 @@ class _RTIOBankI(Module):
class RTIO(Module, AutoCSR):
def __init__(self, phy, clk_freq, counter_width=32,
def __init__(self, phy, clk_freq, counter_width=63,
ofifo_depth=64, ififo_depth=64,
guard_io_cycles=20):
fine_ts_width = get_fine_ts_width(phy.rbus)

1
soc/targets/artiq_ppro.py
View File

@ -119,6 +119,7 @@ class ARTIQMiniSoC(BaseSoC):
output_only_pads=set(rtio_outs))
self.submodules.rtio = rtio.RTIO(self.rtiophy,
clk_freq=125000000,
counter_width=32,
ififo_depth=512)
rtio_csrs = self.rtio.get_csrs()