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rtio: collision_error -> collision
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commit
71105fd0d7
@ -10,3 +10,5 @@ Release notes
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* Core device flash storage has moved due to increased runtime size.
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This requires reflashing the runtime and the flash storage filesystem image
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or erase and rewrite its entries.
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* RTIOCollisionError has been renamed to RTIOCollision
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@ -1,12 +1,12 @@
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from artiq.coredevice import exceptions, dds, spi
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from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
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RTIOCollisionError, RTIOOverflow,
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RTIOCollision, RTIOOverflow,
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DDSBatchError, CacheError)
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from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
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PHASE_MODE_TRACKING)
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__all__ = []
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__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError",
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__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollision",
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"RTIOOverflow", "DDSBatchError", "CacheError"]
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__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
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"PHASE_MODE_TRACKING"]
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@ -86,7 +86,7 @@ class RTIOSequenceError(Exception):
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"""
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artiq_builtin = True
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class RTIOCollisionError(Exception):
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class RTIOCollision(Exception):
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"""Raised when an event is submitted on a given channel with the same
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coarse timestamp as the previous one but with a different fine timestamp.
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@ -82,7 +82,7 @@ class MessageEncoder(Module, AutoCSR):
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rtio_core.counter.value_sys << rtio_core.fine_ts_width),
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]
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for ename in ("o_underflow_reset", "o_sequence_error_reset",
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"o_collision_error_reset", "i_overflow_reset"):
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"o_collision_reset", "i_overflow_reset"):
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self.comb += \
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If(getattr(kcsrs, ename).re,
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exception_stb.eq(1),
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@ -103,7 +103,7 @@ class _OutputManager(Module):
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self.underflow = Signal() # valid 1 cycle after we, pulsed
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self.sequence_error = Signal()
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self.collision_error = Signal()
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self.collision = Signal()
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# # #
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@ -126,7 +126,7 @@ class _OutputManager(Module):
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# Special cases
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replace = Signal()
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sequence_error = Signal()
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collision_error = Signal()
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collision = Signal()
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any_error = Signal()
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nop = Signal()
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self.sync.rsys += [
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@ -140,10 +140,10 @@ class _OutputManager(Module):
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< buf.timestamp[fine_ts_width:])
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]
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if fine_ts_width:
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self.sync.rsys += collision_error.eq(
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self.sync.rsys += collision.eq(
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& (self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width]))
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self.comb += any_error.eq(sequence_error | collision_error)
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self.comb += any_error.eq(sequence_error | collision)
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if interface.suppress_nop:
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# disable NOP at reset: do not suppress a first write with all 0s
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nop_en = Signal(reset=0)
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@ -163,7 +163,7 @@ class _OutputManager(Module):
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]
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self.comb += [
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self.sequence_error.eq(self.we & sequence_error),
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self.collision_error.eq(self.we & collision_error)
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self.collision.eq(self.we & collision)
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]
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# Buffer read and FIFO write
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@ -335,7 +335,7 @@ class _KernelCSRs(AutoCSR):
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self.o_status = CSRStatus(4)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_collision_error_reset = CSR()
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self.o_collision_reset = CSR()
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if data_width:
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self.i_data = CSRStatus(data_width)
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@ -422,22 +422,22 @@ class RTIO(Module):
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underflow = Signal()
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sequence_error = Signal()
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collision_error = Signal()
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collision = Signal()
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self.sync.rsys += [
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If(selected & self.kcsrs.o_underflow_reset.re,
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underflow.eq(0)),
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If(selected & self.kcsrs.o_sequence_error_reset.re,
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sequence_error.eq(0)),
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If(selected & self.kcsrs.o_collision_error_reset.re,
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collision_error.eq(0)),
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If(selected & self.kcsrs.o_collision_reset.re,
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collision.eq(0)),
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If(o_manager.underflow, underflow.eq(1)),
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If(o_manager.sequence_error, sequence_error.eq(1)),
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If(o_manager.collision_error, collision_error.eq(1))
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If(o_manager.collision, collision.eq(1))
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]
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o_statuses.append(Cat(~o_manager.writable,
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underflow,
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sequence_error,
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collision_error))
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collision))
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if channel.interface.i is not None:
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i_manager = _InputManager(channel.interface.i, self.counter,
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@ -15,6 +15,6 @@ class ExceptionType(Enum):
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o_underflow_reset = 0b010000
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o_sequence_error_reset = 0b010001
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o_collision_error_reset = 0b010010
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o_collision_reset = 0b010010
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i_overflow_reset = 0b100000
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@ -33,10 +33,10 @@ static void rtio_process_exceptional_status(
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"RTIO sequence error at {0} mu, channel {1}",
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timestamp, channel, 0);
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}
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if(status & RTIO_O_STATUS_COLLISION_ERROR) {
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rtio_o_collision_error_reset_write(1);
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artiq_raise_from_c("RTIOCollisionError",
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"RTIO collision error at {0} mu, channel {1}",
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if(status & RTIO_O_STATUS_COLLISION) {
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rtio_o_collision_reset_write(1);
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artiq_raise_from_c("RTIOCollision",
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"RTIO collision at {0} mu, channel {1}",
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timestamp, channel, 0);
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}
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}
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@ -6,7 +6,7 @@
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#define RTIO_O_STATUS_FULL 1
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#define RTIO_O_STATUS_UNDERFLOW 2
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#define RTIO_O_STATUS_SEQUENCE_ERROR 4
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#define RTIO_O_STATUS_COLLISION_ERROR 8
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#define RTIO_O_STATUS_COLLISION 8
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#define RTIO_I_STATUS_EMPTY 1
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#define RTIO_I_STATUS_OVERFLOW 2
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@ -150,7 +150,7 @@ class SequenceError(EnvExperiment):
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self.ttl_out.pulse(25*us)
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class CollisionError(EnvExperiment):
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class Collision(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ttl_out_serdes")
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@ -220,9 +220,9 @@ class CoredeviceTest(ExperimentCase):
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with self.assertRaises(RTIOSequenceError):
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self.execute(SequenceError)
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def test_collision_error(self):
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with self.assertRaises(RTIOCollisionError):
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self.execute(CollisionError)
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def test_collision(self):
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with self.assertRaises(RTIOCollision):
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self.execute(Collision)
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def test_watchdog(self):
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# watchdog only works on the device
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