mirror of https://github.com/m-labs/artiq.git
sawg: clean up Config
* unify I and Q data limiters. there is no conceivable way why they would be different. * reorder clr bits to be like consistent * move the sat add limiter to before the hbf again
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f4c6879c76
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4b3aad2563
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@ -10,12 +10,10 @@ _SAWG_DIV = 0
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_SAWG_CLR = 1
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_SAWG_IQ_EN = 2
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# _SAWF_PAD = 3 # reserved
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_SAWG_DUC_I_MIN = 4
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_SAWG_DUC_I_MAX = 5
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_SAWG_DUC_Q_MIN = 6
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_SAWG_DUC_Q_MAX = 7
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_SAWG_OUT_MIN = 8
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_SAWG_OUT_MAX = 9
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_SAWG_OUT_MIN = 4
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_SAWG_OUT_MAX = 5
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_SAWG_DUC_MIN = 6
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_SAWG_DUC_MAX = 7
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class Config:
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@ -92,8 +90,8 @@ class Config:
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:param clr2: Auto-clear phase accumulator of the ``phase2``/
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``frequency2`` DDS. Default: ``True``
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"""
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rtio_output(now_mu(), self.channel, _SAWG_CLR, clr1 |
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(clr2 << 1) | (clr0 << 2))
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rtio_output(now_mu(), self.channel, _SAWG_CLR, clr0 |
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(clr1 << 1) | (clr2 << 2))
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@kernel
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def set_iq_en(self, i_enable: TInt32, q_enable: TInt32):
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@ -122,48 +120,38 @@ class Config:
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(q_enable << 1))
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@kernel
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def set_duc_i_max_mu(self, limit: TInt32):
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"""Set the digital up-converter (DUC) I data summing junction upper
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limit. In machine units.
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def set_duc_max_mu(self, limit: TInt32):
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"""Set the digital up-converter (DUC) I and Q data summing junctions
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upper limit. In machine units.
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The default limits are chosen to reach maximum and minimum DAC output
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amplitude.
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For a description of the limiter functions in normalized units see:
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.. seealso:: :meth:`set_duc_i_max`
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.. seealso:: :meth:`set_duc_max`
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"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_I_MAX, limit)
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rtio_output(now_mu(), self.channel, _SAWG_DUC_MAX, limit)
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@kernel
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def set_duc_i_min_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_I_MIN, limit)
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@kernel
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def set_duc_q_max_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_Q_MAX, limit)
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@kernel
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def set_duc_q_min_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_Q_MIN, limit)
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def set_duc_min_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_MIN, limit)
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@kernel
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def set_out_max_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max_mu`"""
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""".. seealso:: :meth:`set_duc_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_OUT_MAX, limit)
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@kernel
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def set_out_min_mu(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max_mu`"""
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""".. seealso:: :meth:`set_duc_max_mu`"""
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rtio_output(now_mu(), self.channel, _SAWG_OUT_MIN, limit)
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@kernel
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def set_duc_i_max(self, limit: TFloat):
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"""Set the digital up-converter (DUC) I data summing junction upper
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limit.
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def set_duc_max(self, limit: TFloat):
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"""Set the digital up-converter (DUC) I and Q data summing junctions
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upper limit.
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Each of the three summing junctions has a saturating adder with
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configurable upper and lower limits. The three summing junctions are:
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@ -171,7 +159,8 @@ class Config:
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* At the in-phase input to the ``phase0``/``frequency0`` fast DUC,
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after the anti-aliasing FIR filter.
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* At the quadrature input to the ``phase0``/``frequency0``
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fast DUC, after the anti-aliasing FIR filter.
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fast DUC, after the anti-aliasing FIR filter. The in-phase and
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quadrature data paths both use the same limits.
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* Before the DAC, where the following three data streams
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are added together:
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@ -190,42 +179,28 @@ class Config:
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``[-1, 1]``.
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.. seealso::
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* :meth:`set_duc_i_max`: Upper limit of the in-phase input to
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the DUC.
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* :meth:`set_duc_i_min`: Lower limit of the in-phase input to
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the DUC.
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* :meth:`set_duc_q_max`: Upper limit of the quadrature input to
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the DUC.
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* :meth:`set_duc_q_min`: Lower limit of the quadrature input to
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the DUC.
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* :meth:`set_duc_max`: Upper limit of the in-phase and quadrature
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inputs to the DUC.
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* :meth:`set_duc_min`: Lower limit of the in-phase and quadrature
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inputs to the DUC.
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* :meth:`set_out_max`: Upper limit of the DAC output.
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* :meth:`set_out_min`: Lower limit of the DAC output.
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"""
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self.set_duc_i_max_mu(int32(round(limit*self._duc_scale)))
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self.set_duc_max_mu(int32(round(limit*self._duc_scale)))
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@kernel
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def set_duc_i_min(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_i_max`"""
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self.set_duc_i_min_mu(int32(round(limit*self._duc_scale)))
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@kernel
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def set_duc_q_max(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_i_max`"""
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self.set_duc_q_max_mu(int32(round(limit*self._duc_scale)))
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@kernel
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def set_duc_q_min(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_i_max`"""
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self.set_duc_q_min_mu(int32(round(limit*self._duc_scale)))
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def set_duc_min(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_max`"""
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self.set_duc_min_mu(int32(round(limit*self._duc_scale)))
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@kernel
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def set_out_max(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_i_max`"""
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""".. seealso:: :meth:`set_duc_max`"""
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self.set_out_max_mu(int32(round(limit*self._out_scale)))
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@kernel
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def set_out_min(self, limit: TFloat):
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""".. seealso:: :meth:`set_duc_i_max`"""
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""".. seealso:: :meth:`set_duc_max`"""
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self.set_out_min_mu(int32(round(limit*self._out_scale)))
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@ -306,6 +281,7 @@ class SAWG:
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width = 16
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time_width = 16
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cordic_gain = 1.646760258057163 # Cordic(width=16, guard=None).gain
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cordic_gain *= 1.01 # leave a bit of headroom
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self.config = Config(channel_base, self.core, cordic_gain)
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self.offset = Spline(width, time_width, channel_base + 1,
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self.core, 2.)
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@ -335,7 +311,7 @@ class SAWG:
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settings.
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This method advances the timeline by the time required to perform all
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eight writes to the configuration channel.
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six writes to the configuration channel.
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"""
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self.frequency0.set_mu(0)
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self.frequency1.set_mu(0)
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@ -350,13 +326,9 @@ class SAWG:
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delay_mu(self.config._rtio_interval)
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self.config.set_iq_en(1, 0)
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delay_mu(self.config._rtio_interval)
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self.config.set_duc_i_min(-1.)
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self.config.set_duc_min(-1.)
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delay_mu(self.config._rtio_interval)
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self.config.set_duc_i_max(1.)
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delay_mu(self.config._rtio_interval)
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self.config.set_duc_q_min(-1.)
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delay_mu(self.config._rtio_interval)
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self.config.set_duc_q_max(1.)
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self.config.set_duc_max(1.)
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delay_mu(self.config._rtio_interval)
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self.config.set_out_min(-1.)
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delay_mu(self.config._rtio_interval)
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@ -83,35 +83,43 @@ class SplineParallelDDS(SplineParallelDUC):
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class Config(Module):
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def __init__(self, width):
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def __init__(self, width, cordic_gain):
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self.clr = Signal(3, reset=0b111)
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self.iq_en = Signal(2, reset=0b01)
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self.limits = [[Signal((width, True), reset=-(1 << width - 1)),
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Signal((width, True), reset=(1 << width - 1) - 1)]
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for i in range(3)]
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self.clipped = [Signal(2) for i in range(3)] # TODO
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self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limits))),
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("data", 16)])
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self.limits = [[Signal((width, True)), Signal((width, True))]
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for i in range(2)]
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limit = 1 << width - 1
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self.limits[0][0].reset = -limit
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self.limits[0][1].reset = limit - 1
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self.limits[1][0].reset = int(-limit/cordic_gain)
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self.limits[1][1].reset = int((limit - 1)/cordic_gain)
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# TODO make persistent, add read-out/notification/clear
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self.clipped = [Signal(2) for i in range(2)]
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self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limits) - 1)),
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("data", width)])
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assert len(self.i.addr) == 3
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self.ce = Signal()
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###
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div = Signal(16, reset=0)
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n = Signal.like(div)
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pad = Signal()
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reg = Array([Cat(div, n), self.clr, self.iq_en, pad] +
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sum(self.limits, []))
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self.comb += [
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self.i.ack.eq(1),
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self.ce.eq(n == 0),
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]
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self.comb += self.ce.eq(n == 0)
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self.sync += [
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n.eq(n - 1),
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If(self.ce,
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n.eq(div),
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),
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)
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]
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pad = Signal()
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reg = Array(sum(self.limits,
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[Cat(div, n), self.clr, self.iq_en, pad]))
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self.comb += self.i.ack.eq(1)
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self.sync += [
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If(self.i.stb,
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reg[self.i.addr].eq(self.i.data),
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),
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@ -131,26 +139,26 @@ class Channel(Module, SatAddMixin):
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coeff = halfgen4_cascade(parallelism, width=.4, order=8)
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hbf = [ParallelHBFUpsampler(coeff, width=width + 1) for i in range(2)]
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self.submodules.b = b = SplineParallelDUC(
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widths._replace(a=len(hbf[0].o[0]), f=widths.f - width), orders,
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widths._replace(a=width + 1, f=widths.f - width), orders,
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parallelism=parallelism)
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cfg = Config(width)
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cfg = Config(width, b.gain)
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u = Spline(width=widths.a, order=orders.a)
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self.submodules += cfg, u, hbf
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self.u = u.tri(widths.t)
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self.i = [cfg.i, self.u, a1.a, a1.f, a1.p, a2.a, a2.f, a2.p, b.f, b.p]
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self.i_names = "cfg u a1 f1 p1 a2 f2 p2 f0 p0".split()
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self.i_named = dict(zip(self.i_names, self.i))
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self.y_in = [Signal((width, True)) for i in range(parallelism)]
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self.y_in = [Signal.like(b.yo[0]) for i in range(parallelism)]
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self.o = [Signal((width, True)) for i in range(parallelism)]
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self.widths = widths
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self.orders = orders
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self.parallelism = parallelism
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self.cordic_gain = a1.gain*b.gain
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self.cordic_gain = a2.gain*b.gain
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self.u.latency += 1
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b.p.latency += 2
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b.f.latency += 2
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a_latency_delta = hbf[0].latency + b.latency + 3
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a_latency_delta = hbf[0].latency + b.latency + 2
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for a in a1, a2:
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a.a.latency += a_latency_delta
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a.p.latency += a_latency_delta
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@ -169,26 +177,19 @@ class Channel(Module, SatAddMixin):
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a2.ce.eq(cfg.ce),
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b.ce.eq(cfg.ce),
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u.o.ack.eq(cfg.ce),
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Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
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Cat(b.clr, a1.clr, a2.clr).eq(cfg.clr),
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]
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self.sync += [
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hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
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limits=cfg.limits[1], clipped=cfg.clipped[1])),
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hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
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limits=cfg.limits[1], clipped=None)), # ignore Q clip data
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]
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for i in range(parallelism):
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self.sync += [
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b.xi[i].eq(self.sat_add(hbf[0].o[i],
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limits=cfg.limits[0],
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clipped=cfg.clipped[0])),
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b.yi[i].eq(self.sat_add(hbf[1].o[i],
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limits=cfg.limits[1],
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clipped=cfg.clipped[1])),
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self.comb += [
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b.xi[i].eq(hbf[0].o[i]),
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b.yi[i].eq(hbf[1].o[i]),
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]
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for i in range(2):
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for j in range(2):
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# correct pre-DUC limiter by cordic gain
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v = cfg.limits[i][j].reset.value
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cfg.limits[i][j].reset.value = int(v / b.gain)
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self.sync += [
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hbf[0].i.eq(a1.xo[0] + a2.xo[0]),
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hbf[1].i.eq(a1.yo[0] + a2.yo[0])
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]
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# wire up outputs and q_{i,o} exchange
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for o, x, y in zip(self.o, b.xo, self.y_in):
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self.sync += [
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@ -196,8 +197,8 @@ class Channel(Module, SatAddMixin):
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u.o.a0[-len(o):],
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Mux(cfg.iq_en[0], x, 0),
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Mux(cfg.iq_en[1], y, 0),
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limits=cfg.limits[2],
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clipped=cfg.clipped[2])),
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limits=cfg.limits[0],
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clipped=cfg.clipped[0])),
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]
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def connect_y(self, buddy):
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