kc705: move ttl channels together again, update doc

artiq/gateware/targets/kc705.py

@@ -256,6 +256,10 @@ class NIST_CLOCK(_NIST_Ions):
         rtio_channels.append(rtio.Channel.from_phy(phy))
         self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
 
+        phy = ttl_simple.ClockGen(platform.request("la32_p"))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
         phy = spi.SPIMaster(ams101_dac)
         self.submodules += phy
         self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
@@ -268,10 +272,6 @@ class NIST_CLOCK(_NIST_Ions):
             rtio_channels.append(rtio.Channel.from_phy(
                 phy, ofifo_depth=128, ififo_depth=128))
 
-        phy = ttl_simple.ClockGen(platform.request("la32_p"))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
         self.config["DDS_CHANNEL_COUNT"] = 11
         self.config["DDS_AD9914"] = True

doc/manual/core_device.rst

@@ -64,7 +64,9 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
 +--------------------+-----------------------+--------------+
 | 19                 | LED                   | Output       |
 +--------------------+-----------------------+--------------+
-| 20                 | LA32_P                | Clock        |
+| 20                 | AMS101_LDAC_B         | Output       |
++--------------------+-----------------------+--------------+
+| 21                 | LA32_P                | Clock        |
 +--------------------+-----------------------+--------------+
 
 
@@ -101,6 +103,4 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are
 
 The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
 
-The board can accept an external RTIO clock connected to PMT2. If the DDS box
-does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output
-on the adapter board onto C:15 disconnecting PMT2.
+The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2.

examples/master/device_db.pyon

@@ -87,24 +87,24 @@
         "class": "TTLOut",
         "arguments": {"channel": 20}
     },
-    "ams101_spi": {
+    "ttl_clock_la32_p": {
         "type": "local",
-        "module": "artiq.coredevice.spi",
-        "class": "SPIMaster",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLClockGen",
         "arguments": {"channel": 21}
     },
 
-    "spi0": {
+    "ams101_spi": {
         "type": "local",
         "module": "artiq.coredevice.spi",
         "class": "SPIMaster",
         "arguments": {"channel": 22}
     },
 
-    "ttl_clock_la32_p": {
+    "spi0": {
         "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLClockGen",
+        "module": "artiq.coredevice.spi",
+        "class": "SPIMaster",
         "arguments": {"channel": 23}
     },