mirror of https://github.com/m-labs/artiq.git
perform RTIO init on comms CPU side
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@ -17,6 +17,9 @@ class _CSRs(AutoCSR):
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self.set_time = CSR()
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self.underflow_margin = CSRStorage(16, reset=200)
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self.reset = CSR()
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self.reset_phy = CSR()
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self.o_get_fifo_space = CSR()
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self.o_dbg_fifo_space = CSRStatus(16)
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self.o_dbg_last_timestamp = CSRStatus(64)
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@ -57,11 +60,11 @@ class RTController(Module):
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# reset
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self.sync += [
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If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
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If(self.cri.cmd == cri.commands["reset"],
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If(self.csrs.reset.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(0)
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),
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If(self.cri.cmd == cri.commands["reset_phy"],
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If(self.csrs.reset_phy.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(1)
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),
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@ -78,8 +78,7 @@ class MessageEncoder(Module, AutoCSR):
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exception.channel.eq(kcsrs.chan_sel.storage),
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exception.rtio_counter.eq(rtio_counter),
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]
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for ename in ("reset", "reset_phy",
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"o_underflow_reset", "o_sequence_error_reset",
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for ename in ("o_underflow_reset", "o_sequence_error_reset",
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"o_collision_reset", "i_overflow_reset"):
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self.comb += \
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If(getattr(kcsrs, ename).re,
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@ -5,6 +5,7 @@ from migen import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri, rtlink
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from artiq.gateware.rtio.cdc import *
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@ -264,13 +265,15 @@ class LogChannel:
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self.overrides = []
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class Core(Module):
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class Core(Module, AutoCSR):
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def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
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if fine_ts_width is None:
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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for c in channels)
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self.cri = cri.Interface()
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self.reset = CSR()
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self.reset_phy = CSR()
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self.comb += self.cri.arb_gnt.eq(1)
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# Clocking/Reset
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@ -279,8 +282,8 @@ class Core(Module):
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cmd_reset = Signal(reset=1)
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cmd_reset_phy = Signal(reset=1)
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self.sync += [
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cmd_reset.eq(self.cri.cmd == cri.commands["reset"]),
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cmd_reset_phy.eq(self.cri.cmd == cri.commands["reset_phy"])
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cmd_reset.eq(self.reset.re),
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cmd_reset_phy.eq(self.reset_phy.re)
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]
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cmd_reset.attr.add("no_retiming")
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cmd_reset_phy.attr.add("no_retiming")
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@ -8,17 +8,15 @@ from misoc.interconnect.csr import *
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commands = {
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"nop": 0,
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"reset": 1,
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"reset_phy": 2,
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"write": 3,
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"read": 4,
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"write": 1,
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"read": 2,
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"o_underflow_reset": 5,
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"o_sequence_error_reset": 6,
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"o_collision_reset": 7,
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"o_busy_reset": 8,
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"i_overflow_reset": 9
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"o_underflow_reset": 3,
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"o_sequence_error_reset": 4,
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"o_collision_reset": 5,
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"o_busy_reset": 6,
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"i_overflow_reset": 7
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}
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@ -57,8 +55,6 @@ class KernelInitiator(Module, AutoCSR):
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self.arb_req = CSRStorage()
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self.arb_gnt = CSRStatus()
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self.reset = CSR()
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self.reset_phy = CSR()
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self.chan_sel = CSRStorage(24)
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self.o_data = CSRStorage(512, write_from_dev=True)
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@ -91,8 +87,6 @@ class KernelInitiator(Module, AutoCSR):
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self.arb_gnt.status.eq(self.cri.arb_gnt),
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self.cri.cmd.eq(commands["nop"]),
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If(self.reset.re, self.cri.cmd.eq(commands["reset"])),
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If(self.reset_phy.re, self.cri.cmd.eq(commands["reset_phy"])),
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If(self.o_we.re, self.cri.cmd.eq(commands["write"])),
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If(self.i_re.re, self.cri.cmd.eq(commands["read"])),
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If(self.o_underflow_reset.re, self.cri.cmd.eq(commands["o_underflow_reset"])),
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@ -144,6 +144,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.register_kernel_cpu_csrdevice("rtio")
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@ -218,6 +218,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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# RTIO logic
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
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self.register_kernel_cpu_csrdevice("rtio")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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@ -9,9 +9,9 @@ class MessageType(Enum):
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class ExceptionType(Enum):
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reset = 0b000000
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legacy_reset = 0b000000
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legacy_reset_falling = 0b000001
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reset_phy = 0b000010
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legacy_reset_phy = 0b000010
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legacy_reset_phy_falling = 0b000011
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o_underflow_reset = 0b010000
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@ -1,6 +1,11 @@
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#[path = "../src/kernel_proto.rs"]
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mod kernel_proto;
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use board::csr;
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use core::ptr::{read_volatile, write_volatile};
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use ::ArtiqList;
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use ::send;
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use kernel_proto::*;
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const RTIO_O_STATUS_FULL: u32 = 1;
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const RTIO_O_STATUS_UNDERFLOW: u32 = 2;
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@ -11,9 +16,7 @@ const RTIO_I_STATUS_EMPTY: u32 = 1;
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const RTIO_I_STATUS_OVERFLOW: u32 = 2;
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pub extern fn init() {
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unsafe {
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csr::rtio::reset_write(1);
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}
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send(&RTIOInitRequest);
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}
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pub extern fn get_counter() -> i64 {
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@ -30,6 +30,8 @@ pub enum Message<'a> {
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NowInitReply(u64),
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NowSave(u64),
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RTIOInitRequest,
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RunFinished,
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RunException {
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exception: Exception<'a>,
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@ -4,6 +4,7 @@ use std::cell::RefCell;
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use std::io::{self, Read, Write, BufWriter};
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use std::btree_set::BTreeSet;
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use {config, rtio_crg, clock, mailbox, rpc_queue, kernel};
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use board::csr; // TODO: centralize (D)RTIO management
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use logger::BufferLogger;
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use cache::Cache;
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use urc::Urc;
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@ -377,6 +378,14 @@ fn process_kern_message(waiter: Waiter,
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kern_acknowledge()
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}
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&kern::RTIOInitRequest => {
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info!("resetting RTIO");
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unsafe {
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csr::rtio_core::reset_write(1);
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}
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kern_acknowledge()
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}
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&kern::WatchdogSetRequest { ms } => {
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let id = try!(session.watchdog_set.set_ms(ms)
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.map_err(|()| io_error("out of watchdogs")));
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