rtio: always read full DMA sequence

2016-12-06 01:05:47 +08:00 · 2016-12-06 01:05:47 +08:00 · f3c50a37ca
parent c413d95b49
commit f3c50a37ca
1 changed files with 2 additions and 2 deletions
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@ -350,12 +350,12 @@ class DMA(Module):
        self.submodules += fsm

        fsm.act("IDLE",
-            If(self.enable.re & self.enable.r, NextState("FLOWING"))
+            If(self.enable.re, NextState("FLOWING"))
        )
        fsm.act("FLOWING",
            self.enable.w.eq(1),
            flow_enable.eq(1),
-            If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
+            If(self.slicer.end_marker_found,
                NextState("FLUSH")
            )
        )