fir: simplify latency compensation

Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.

artiq/gateware/dsp/fir.py

@@ -165,7 +165,7 @@ class ParallelHBFUpsampler(Module):
             self.parallelism *= 2
             hbf = ParallelFIR(coeff, self.parallelism, width, **kwargs)
             self.submodules += hbf
-            self.comb += [a.eq(b) for a, b in zip(hbf.i[::2], i)]
+            self.comb += [a.eq(b) for a, b in zip(hbf.i[1::2], i)]
             i = hbf.o
             self.latency += hbf.latency
         self.o = i