M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-20 00:46:30 +08:00
Code Issues Projects Releases Wiki Activity

rtio: auto clear output event data and address

Browse Source 
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.

Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
This commit is contained in:
Robert Jördens 2016-11-19 14:16:06 +01:00
parent b714137f76
commit 97a54046e8
1 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
artiq/gateware/rtio/core.py
View File

@ -334,9 +334,9 @@ class _KernelCSRs(AutoCSR):
self.chan_sel = CSRStorage(chan_sel_width)
if data_width:
self.o_data = CSRStorage(data_width)
self.o_data = CSRStorage(data_width, write_from_dev=True)
if address_width:
self.o_address = CSRStorage(address_width)
self.o_address = CSRStorage(address_width, write_from_dev=True)
self.o_timestamp = CSRStorage(full_ts_width)
self.o_we = CSR()
self.o_status = CSRStatus(5)
@ -498,5 +498,13 @@ class RTIO(Module):
<< fine_ts_width)
)
# Auto clear/zero pad event data
self.comb += [
self.kcsrs.o_data.dat_w.eq(0),
self.kcsrs.o_data.we.eq(self.kcsrs.o_timestamp.re),
self.kcsrs.o_address.dat_w.eq(0),
self.kcsrs.o_address.we.eq(self.kcsrs.o_timestamp.re),
]
def get_csrs(self):
return self.kcsrs.get_csrs()