mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 19:28:26 +08:00
drtio: fixes
This commit is contained in:
parent
45621934fd
commit
929a7650a8
@ -48,17 +48,18 @@ class IOT(Module):
|
||||
# FIFO write
|
||||
self.comb += fifo.we.eq(rt_packets.write_stb
|
||||
& (rt_packets.write_channel == n))
|
||||
self.sync += \
|
||||
self.sync += [
|
||||
If(rt_packets.write_overflow_ack,
|
||||
rt_packets.write_overflow.eq(0)),
|
||||
If(rt_packets.write_underflow_ack,
|
||||
rt_packets.write_underflow.eq(0)),
|
||||
If(fifo.we,
|
||||
If(rt_packets.write_overflow_ack,
|
||||
rt_packets.write_overflow.eq(0)),
|
||||
If(~fifo.writable, rt_packets.write_overflow.eq(1)),
|
||||
If(rt_packets.write_underflow_ack,
|
||||
rt_packets.write_underflow.eq(0)),
|
||||
If(rt_packets.write_timestamp[max_fine_ts_width:] < (tsc + 4),
|
||||
rt_packets.write_underflow.eq(1)
|
||||
)
|
||||
)
|
||||
]
|
||||
if data_width:
|
||||
self.comb += fifo_in.data.eq(rt_packets.write_data)
|
||||
if address_width:
|
||||
|
@ -48,7 +48,7 @@ class RTController(Module):
|
||||
self.comb += [
|
||||
rt_packets.tsc_value.eq(
|
||||
self.counter.value_rtio + tsc_correction),
|
||||
self.kcsrs.set_time.r.eq(rt_packets.set_time_stb)
|
||||
self.kcsrs.set_time.w.eq(rt_packets.set_time_stb)
|
||||
]
|
||||
self.sync += [
|
||||
If(rt_packets.set_time_ack, rt_packets.set_time_stb.eq(0)),
|
||||
@ -98,8 +98,7 @@ class RTController(Module):
|
||||
cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
|
||||
cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:]
|
||||
- self.kcsrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
|
||||
cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:]
|
||||
< self.counter.value_sys - self.kcsrs.underflow_margin.storage[fine_ts_width:])
|
||||
cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys)
|
||||
& (last_timestamps.dat_r != 0))
|
||||
|
||||
fsm.act("IDLE",
|
||||
|
Loading…
Reference in New Issue
Block a user