mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)
This commit is contained in:
parent
e0ed99cd7b
commit
7a2405146a
@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
|
||||
|
||||
class _AD9xxx(Module):
|
||||
def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
|
||||
self.submodules._ll = ClockDomainsRenamer("rio")(
|
||||
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
|
||||
ad9xxx.AD9xxx(pads, **kwargs))
|
||||
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
|
||||
self.rtlink = self._rt2wb.rtlink
|
||||
|
@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
|
||||
|
||||
class SPIMaster(Module):
|
||||
def __init__(self, pads, **kwargs):
|
||||
self.submodules._ll = ClockDomainsRenamer("rio")(
|
||||
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
|
||||
SPIMasterWB(pads, **kwargs))
|
||||
self.submodules._rt2wb = RT2WB(2, self._ll.bus)
|
||||
self.rtlink = self._rt2wb.rtlink
|
||||
|
Loading…
Reference in New Issue
Block a user