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rtio: break DMA timing path
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ea7549cfa4
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@ -226,9 +226,9 @@ class TimeOffset(Module, AutoCSR):
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# # #
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pipe_ce = Signal()
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self.sync += \
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If(pipe_ce,
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self.sync += [
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If(self.source.ack, self.source.stb.eq(0)),
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If(~self.source.stb,
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self.sink.payload.connect(self.source.payload,
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leave_out={"timestamp"}),
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self.source.payload.timestamp.eq(self.sink.payload.timestamp
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@ -236,10 +236,8 @@ class TimeOffset(Module, AutoCSR):
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self.source.eop.eq(self.sink.eop),
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self.source.stb.eq(self.sink.stb)
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)
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self.comb += [
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pipe_ce.eq(self.source.ack | ~self.source.stb),
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self.sink.ack.eq(pipe_ce)
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]
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self.comb += self.sink.ack.eq(~self.source.stb)
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class CRIMaster(Module, AutoCSR):
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