M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

style

This commit is contained in:
Sebastien Bourdeauducq 2017-09-15 15:36:46 +08:00
parent 8e5ab90129
commit 3c922463a0
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/gateware/rtio/sed/tsc_gate.py
View File

@ -6,7 +6,6 @@ from artiq.gateware.rtio.sed import layouts
__all__ = ["TSCGate"]
class TSCGate(Module):
def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))